Patents by Inventor Shravan Siddartha Nagam

Shravan Siddartha Nagam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Compact phase-locked loop with low jitter and reference spurs
    Patent number: 10615803
    Abstract: The present disclosure relates to a phase-locked loop (PLL) including a frequency detector, a sub-sampling phase detector (SSPD), and a voltage-controlled oscillator (VCO). The frequency detector is configured to receive a reference signal and an output signal, and to generate a coarse-tuning voltage that indicates a frequency difference between the reference signal and the output signal. The SSPD is configured to sub-sample the output signal using the reference signal, and to generate a fine-tuning voltage that indicates a phase difference between the reference signal and the output signal. The VCO is configured to update the output signal based on the coarse-tuning voltage and the fine-tuning voltage.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: April 7, 2020
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Shravan Siddartha Nagam, Peter R. Kinget
  • COMPACT PHASE-LOCKED LOOP WITH LOW JITTER AND REFERENCE SPURS
    Publication number: 20200028515
    Abstract: The present disclosure relates to a phase-locked loop (PLL) including a frequency detector, a sub-sampling phase detector (SSPD), and a voltage-controlled oscillator (VCO). The frequency detector is configured to receive a reference signal and an output signal, and to generate a coarse-tuning voltage that indicates a frequency difference between the reference signal and the output signal. The SSPD is configured to sub-sample the output signal using the reference signal, and to generate a fine-tuning voltage that indicates a phase difference between the reference signal and the output signal. The VCO is configured to update the output signal based on the coarse-tuning voltage and the fine-tuning voltage.
    Type: Application
    Filed: July 23, 2018
    Publication date: January 23, 2020
    Inventors: Shravan Siddartha Nagam, Peter R. Kinget