Patents by Inventor Shravya Gottipati

Shravya Gottipati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Tailoring timing offsets during a programming pulse for a memory device
    Patent number: 10553286
    Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select one or more timing offsets for a programming pulse based on one or more of a polarity of access for the memory cell, a number of prior write cycles for the memory cell, or electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming pulse with the one or more selected timing offset to program the memory cell within the array of memory cells.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Daniel Chu, Shravya Gottipati
  • TAILORING TIMING OFFSETS DURING A PROGRAMMING PULSE FOR A MEMORY DEVICE
    Publication number: 20190043585
    Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select one or more timing offsets for a programming pulse based on one or more of a polarity of access for the memory cell, a number of prior write cycles for the memory cell, or electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming pulse with the one or more selected timing offset to program the memory cell within the array of memory cells.
    Type: Application
    Filed: September 28, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Koushik Banerjee, Daniel Chu, Shravya Gottipati