Patents by Inventor Shree Kant
Shree Kant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8482316Abstract: Circuits, methods, and systems are presented for managing current leakage in an electronic circuit. One circuit includes a keeper circuit, and a controller. The keeper circuit supplies current to a leaker circuit, which is experiencing current leakage, to compensate for the current leakage. Further, the controller provides to the keeper circuit a control signal that is based on the current leakage. The control signal has a cycle equal to the cycle of a clock signal, and the control signal is a pulse having a first value during a first period, and a second value during a second period of the pulse. The keeper circuit provides a current to the leaker circuit during the first period and the keeper circuit withholds the current to the leaker circuit during the second period, where the durations of the first period and the second period are based on the current leakage.Type: GrantFiled: March 2, 2012Date of Patent: July 9, 2013Assignee: Oracle International CorporationInventors: Zhen Wu Liu, Shree Kant, Heechoul Park
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Patent number: 7484061Abstract: A method and apparatus is provided to enable provision of requested data within two clock cycles when performing a swap operation between an accessible memory cell and a background memory in a computer. In a first clock cycle, memory addresses to be used in the swap operation are decoded. In a high phase of a second clock cycle, requested data is restored from the background memory to an accessible memory cell. Because the data previously stored in the accessible memory cell is duplicated in a shadow memory cell, the restoration of data to the accessible memory cell is performed without data loss. In a low phase of the second clock cycle, the requested data is available for reading. During a third cycle, data is saved from the shadow memory cell to the background memory, and the shadow memory cell is made consistent with the accessible memory cell.Type: GrantFiled: April 6, 2005Date of Patent: January 27, 2009Assignee: Sun Microsystems, Inc.Inventors: Zhen Wu Liu, Shree Kant, Kenway W. Tam
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Patent number: 7337305Abstract: A system and method of processing multiple swap requests including receiving a first swap request in a pipeline and executing the first swap request. A second swap request is also received in the pipeline immediately following the first swap request. The first swap request and the second swap request are examined to determine if the first swap request and the second swap request swap a same register.Type: GrantFiled: November 24, 2003Date of Patent: February 26, 2008Assignee: Sun Microsystems, Inc.Inventors: Kenway W. Tam, Shree Kant
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Patent number: 7203100Abstract: A multi-threaded memory system including a plurality of entries, each one of the plurality of entries including a plurality of threads, each one of the plurality of threads including an active cell and a shared read cell. The shared read cell has an output coupled to a read bit line and a corresponding plurality of inputs coupled to an output of the corresponding active cells in each one of the plurality of threads. A multi-threaded memory system is also described.Type: GrantFiled: January 21, 2005Date of Patent: April 10, 2007Assignee: Sun Mircosystems, Inc.Inventors: Shree Kant, Kathirgamar Aingaran, Yuan-Jung D Lin, Kenway Tam
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Patent number: 7136308Abstract: A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass gate, at least one driver and a bit line. The at least one pass gate and the at least one driver have a device size substantially similar to a device size of each one of the devices in the active storage circuit and the at least one base storage circuit. A method of swapping data between two storage circuits is also described.Type: GrantFiled: November 1, 2004Date of Patent: November 14, 2006Assignee: Sun Microsystems, Inc.Inventors: Shree Kant, Kenway Tam, Poonacha P. Kongetira, Yuan-Jung D Lin, Zhen W. Liu, Kathirgamar Aingaran
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Publication number: 20060092711Abstract: A multi-threaded memory system including a plurality of entries, each one of the plurality of entries including a plurality of threads, each one of the plurality of threads including an active cell and a shared read cell. The shared read cell has an output coupled to a read bit line and a corresponding plurality of inputs coupled to an output of the corresponding active cells in each one of the plurality of threads. A multi-threaded memory system is also described.Type: ApplicationFiled: January 21, 2005Publication date: May 4, 2006Applicant: Sun Microsystems, IncInventors: Shree Kant, Kathirgamar Aingaran, Yuan-Jung Lin, Kenway Tam
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Publication number: 20060092710Abstract: A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass gate, at least one driver and a bit line. The at least one pass gate and the at least one driver have a device size substantially similar to a device size of each one of the devices in the active storage circuit and the at least one base storage circuit. A method of swapping data between two storage circuits is also described.Type: ApplicationFiled: November 1, 2004Publication date: May 4, 2006Applicant: Sun Microsystems, IncInventors: Shree Kant, Kenway Tam, Poonacha Kongetira, Yuang-Jung Lin, Zhen Liu, Kathirgamar Aingaran
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Patent number: 6940771Abstract: A memory array design is provided. Memory cells are defined an intersections of rows and columns. A pair of bitline segments are defined for each column. A connecting load device of each memory cell is connected to either a first or a second of the pair of bitline segments. An equal number of load devices in each column couple to each of the pair of bitlines.Type: GrantFiled: January 30, 2003Date of Patent: September 6, 2005Assignee: Sun Microsystems, Inc.Inventors: Shree Kant, Aparna Ramachandran, Ranjan Vaish
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Patent number: 6900668Abstract: A first sense amp circuit includes a pre-charge circuit, a keeper circuit, a select device and a driver device. The pre-charge circuit coupled to an input data line, the input data line being coupled to an input of a first inverter. The keeper circuit coupled in parallel with the first inverter. The select device coupled to a discharge path of the first inverter. The driver device coupled in parallel to an output data line of the first inverter.Type: GrantFiled: November 24, 2003Date of Patent: May 31, 2005Assignee: Sun Microsystems Inc.Inventors: Kenway W. Tam, Shree Kant
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Publication number: 20050110527Abstract: A first sense amp circuit includes a pre-charge circuit, a keeper circuit, a select device and a driver device. The pre-charge circuit coupled to an input data line, the input data line being coupled to an input of a first inverter. The keeper circuit coupled in parallel with the first inverter. The select device coupled to a discharge path of the first inverter. The driver device coupled in parallel to an output data line of the first inverter.Type: ApplicationFiled: November 24, 2003Publication date: May 26, 2005Applicant: Sun Microsystems, IncInventors: Kenway Tam, Shree Kant
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Publication number: 20050114634Abstract: A system and method of processing multiple swap requests including receiving a first swap request in a pipeline and executing the first swap request. A second swap request is also received in the pipeline immediately following the first swap request. The first swap request and the second swap request are examined to determine if the first swap request and the second swap request swap a same register.Type: ApplicationFiled: November 24, 2003Publication date: May 26, 2005Applicant: Sun Microsystems, Inc.Inventors: Kenway Tam, Shree Kant
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Publication number: 20040151044Abstract: A memory array design is provided. Memory cells are defined an intersections of rows and columns. A pair of bitline segments are defined for each column. A connecting load device of each memory cell is connected to either a first or a second of the pair of bitline segments. An equal number of load devices in each column couple to each of the pair of bitlines.Type: ApplicationFiled: January 30, 2003Publication date: August 5, 2004Applicant: Sun Microsystems, Inc.Inventors: Shree Kant, Aparna Ramachandran, Ranjan Vaish
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Patent number: 6707721Abstract: A register file design having an asymmetric bit line driver is provided. More specifically, the register file design uses a memory element that has a footer device that facilitates the discharge/charging of a bit line through a pass device, where a width of the footer device is greater than a width of the pass device. Further, a method for performing low power memory operations using asymmetric bit line drivers is provided.Type: GrantFiled: March 13, 2002Date of Patent: March 16, 2004Assignee: Sun Microsystems, Inc.Inventors: Gajendra Singh, Aparna Ramachandran, Miao Rao, Shree Kant
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Patent number: 6646951Abstract: An address decoder having pre-decode logic circuitry positioned in between ends of final decode logic circuitry is provided. Such an address decoder yields less wire load, less gate load, less power consumption, and increased speed due to the pre-decode logic circuitry having to be capable of only driving a signal over half the length of a final decoder. Further, a method to select memory elements from a memory array using centrally positioned pre-decode logic circuitry is provided.Type: GrantFiled: October 23, 2001Date of Patent: November 11, 2003Assignee: Sun Microsystems, Inc.Inventors: Shree Kant, Aparna Ramachandran
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Publication number: 20030174535Abstract: A register file design having an asymmetric bit line driver is provided. More specifically, the register file design uses a memory element that has a footer device that facilitates the discharge/charging of a bit line through a pass device, where a width of the footer device is greater than a width of the pass device. Further, a method for performing low power memory operations using asymmetric bit line drivers is provided.Type: ApplicationFiled: March 13, 2002Publication date: September 18, 2003Inventors: Gajendra Singh, Aparna Ramachandran, Miao Rao, Shree Kant
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Publication number: 20030076732Abstract: An address decoder having pre-decode logic circuitry positioned in between ends of final decode logic circuitry is provided. Such an address decoder yields less wire load, less gate load, less power consumption, and increased speed due to the pre-decode logic circuitry having to be capable of only driving a signal over half the length of a final decoder. Further, a method to select memory elements from a memory array using centrally positioned pre-decode logic circuitry is provided.Type: ApplicationFiled: October 23, 2001Publication date: April 24, 2003Inventors: Shree Kant, Aparna Ramachandran
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Patent number: 6442099Abstract: A method and apparatus for consuming low power when accessing data from a memory array is provided. Further, a method and apparatus for consuming low power when accessing data from a segmented bit line structure in a register file is provided by using transistors having progressively smaller widths as the storage cells or segments they are in get closer to an output of the segmented bit line structure. Further, a method and apparatus for consuming low power when accessing data from a differential bit line structure in a register file is provided by using transistors having progressively smaller widths as the storage cells they are in get closer to an output of the differential bit line structure.Type: GrantFiled: April 18, 2001Date of Patent: August 27, 2002Assignee: Sun Microsystems, Inc.Inventors: Shree Kant, Gajendra P. Singh
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Patent number: 6320813Abstract: Decoding of addresses in a register file is simplified by reducing the number of bits used for addressing by one. Bits are read from even/odd cell combinations simultaneously, and a reserved address line is driven high. The reserved address line is coupled to each driver corresponding to a storage cell. Individual even cells may also be read. Writing to even/odd cell combinations may be performed in a similar manner. However, when writing, an even write enable line and an odd write enable line are provided to indicate whether an even cell, an odd cell, or an even/odd cell combination should be written to simultaneously. By simplifying the decoding stage, performance of reading and writing tasks may be performed much faster and use less resources.Type: GrantFiled: March 2, 2000Date of Patent: November 20, 2001Assignee: Sun Microsystems, Inc.Inventor: Shree Kant
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Patent number: 6316301Abstract: In a logic circuit having PMOS pull-up devices and NMOS pull-down devices, the PMOS pull-up devices are sized relative to the NMOS pull-down devices according to the number of transistors that simultaneously turn on. In one embodiment, the PMOS transistor width is determined by multiplying the effective NMOS transistor width by a predetermined factor indicative of a current carrying ratio between one of the PMOS pull-up transistors and one of the NMOS pull-down transistors and dividing by the number of PMOS pull-up transistors that simultaneously turn on to charge the output node high. Where the PMOS pull-up devices are parallel-connected, the NMOS transistor width is divided by the number of NMOS transistors.Type: GrantFiled: March 8, 2000Date of Patent: November 13, 2001Assignee: Sun Microsystems, Inc.Inventor: Shree Kant
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Patent number: 6038193Abstract: A read system for a multi-ported register file includes a segmented bit line coupled to a global bit line. Each local bit line segment is coupled to a sub-set of the register files in a column to reduce device load and connection load. The local bit line segments are each coupled in series by local sense amps with the local bit line segment coupled to the input of a global sense amplifier. The number of cells coupled to the last bit line segment is more than the number of cells coupled to a bit line segment farthest from the global sense amplifier to balance device and interconnect load and provide for uniform read timing. Both the local bit line segments and global bit line are precharged prior to sensing a bit so that the local sense amplifiers do not require output pull-up transistors. This scheme will not work if the local sense amp includes a pull-up PMOS transistor at its output.Type: GrantFiled: December 23, 1998Date of Patent: March 14, 2000Assignee: Sun Microsystems, Inc.Inventors: Yong Wang, Shree Kant