Abstract: Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.

Abstract: A package comprising a substrate and an integrated device. The substrate includes a core layer comprising a first surface and a second surface; a plurality of core interconnects located in the core layer; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects located in the at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects located in the at least one second dielectric layer; and a capacitor structure located in the core layer. The capacitor structure includes a first trench capacitor device comprising a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, where the second trench capacitor device comprises a second front side and a second back side.

Abstract: A package comprising a substrate, a bridge located in the substrate, a first integrated device coupled to the substrate and a second integrated device coupled to the substrate. The bridge includes a bridge substrate; at least one first bridge dielectric layer coupled to a first surface of the bridge substrate; at least one first bridge interconnect located in the at least one first bridge dielectric layer; at least one second bridge dielectric layer coupled to a second surface of the bridge substrate; at least one second bridge interconnect located in the at least one second bridge dielectric layer; and at least one bridge interconnect that extends through the at least one first bridge dielectric layer and the bridge substrate.

Abstract: A package that includes a substrate, an integrated device coupled to the substrate, and an integrated passive device comprising at least two capacitors. The integrated passive device is coupled to the substrate. The integrated passive device includes a passive device substrate comprising a first trench and a second trench, an oxide layer located over the first trench and the second trench, a first electrically conductive layer located over the oxide layer the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer.

Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first die. The first die includes a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) of the first die. The 3D IC also includes a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die. The 3D IC further includes active circuitry coupled to the 3D stacked capacitor through the PDN of the first die.

Abstract: A package that includes a substrate, an integrated device coupled to the substrate, and an integrated passive device comprising at least two capacitors. The integrated passive device is coupled to the substrate. The integrated passive device includes a passive device substrate comprising a first trench and a second trench, an oxide layer located over the first trench and the second trench, a first electrically conductive layer located over the oxide layer the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer.

Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first die. The first die includes a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) of the first die. The 3D IC also includes a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die. The 3D IC further includes active circuitry coupled to the 3D stacked capacitor through the PDN of the first die.

Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply capacitively couples a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. The low-dropout voltage regulator may include a class-AB operational transconductance amplifier driving the coupling capacitor. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.

Abstract: Some features pertain to an integrated device that includes a die and a first redistribution portion coupled to the die. The first redistribution portion includes at least one dielectric layer and a capacitor. The capacitor includes a first plate, a second plate, and an insulation layer located between the first plate and the second plate. The first redistribution portion further includes several first pins coupled to the first plate of the capacitor. The first redistribution portion further includes several second pins coupled to the second plate of the capacitor. In some implementations, the capacitor includes the first pins and/or the second pins. In some implementations, at least one pin from the several first pins traverses through the second plate to couple to the first plate of the capacitor. In some implementations, the second plate comprises a fin design.

Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, and a redistribution portion coupled to one of the metal layers. The redistribution portion includes a first metal redistribution layer, an insulation layer coupled to the first metal redistribution layer, and a second metal redistribution layer coupled to the insulation layer. The first metal redistribution layer, the insulation layer, and the second metal redistribution layer are configured to operate as a capacitor in the integrated device. In some implementations, the capacitor is a metal-insulator-metal (MIM) capacitor.

Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.

Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.

Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply capacitively couples a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. The low-dropout voltage regulator may include a class-AB operational transconductance amplifier driving the coupling capacitor. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.

Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.

Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.

Abstract: A memory interface includes circuitry configured for applying a variable delay to a portion of a data signal and applying a variable delay to a data strobe. The delayed data strobe samples the delayed portion of the data signal. Delayed portions of the data signal are spaced away from non-delayed portions of the data signal by alternating the routing of delayed bits and non-delayed bits of the data signal. A training block determines and sets a value of the variable delay corresponding to a largest value of a number of recorded eye aperture widths.

Abstract: Aspects of a method of manufacturing a capacitor are provided. The method includes layering a plurality of dielectric plates. The plurality of dielectric plates includes a first dielectric plate having a first conductive region and a second conductive region on a surface of the first dielectric plate. The method further includes forming an inner electrode through an axis of the layered plurality of dielectric plates. The inner electrode electrically couples to the first conductive region on the surface of the first dielectric plate. The method further includes forming an outer electrode, where the outer electrode electrically couples to the second conductive region on the surface of the first dielectric plate.

Abstract: A capacitor with low equivalent series inductance includes multiple electrode layers arranged in parallel with alternating ones of the electrode layers connected together to form the two electrodes of the capacitor. A first set of the electrode layers are connected by an outer wall. A second set of the electrode layers are connected by a central post. Terminals on the capacitor can be spaced on a surface so that signals can be conveniently routed when the capacitor is mounted on or in a printed circuit board or integrated circuit package. Terminals can be included on opposing surfaces of the capacitors to provide for stacking. Additionally, one of the terminals substantially surrounds the other terminal and can provide electromagnetic shielding.

Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, and a redistribution portion coupled to one of the metal layers. The redistribution portion includes a first metal redistribution layer, an insulation layer coupled to the first metal redistribution layer, and a second metal redistribution layer coupled to the insulation layer. The first metal redistribution layer, the insulation layer, and the second metal redistribution layer are configured to operate as a capacitor in the integrated device. In some implementations, the capacitor is a metal-insulator-metal (MIM) capacitor.

Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of horizontal interconnects and gap channels. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. The highest crosstalk may comprise far-end crosstalk or near-end crosstalk and may be calculated for a range of frequencies or for a plurality of frequencies. The crosstalk may be calculated by modeling the interconnects as transmission lines.