Patents by Inventor Shreedhara Maduvinakodi Ramegowda

Shreedhara Maduvinakodi Ramegowda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flow control between fiber channel and wide area networks
    Patent number: 7397764
    Abstract: Multiple fiber channel (FC) storage area networks (SANs) are interconnected over wide-area networks (WANs) to form a long-distance (e.g., greater than about 10 km) distributed storage area network (DSAN) that includes FC to Internet Protocol (IP) over WAN (e.g., SONET or gigabit Ethernet (GE)) gateways that interwork the FC buffer-to-buffer and IP/WAN flow-control mechanisms appropriate to either the SONET or GE link layers using an additive increase, multiplicative decrease (AIMD) congestion avoidance algorithm. The gateways effectively spoof the FC buffer-to-buffer credit mechanism on the FC-interface side of the gateway, while using an IP Internet control message protocol (ICMP) quench mechanism on all WAN links and additionally the IEEE 802.3 pause packet flow control mechanism on gigabit Ethernet (GE) WAN links in combination, in both cases, with a rate-throttling mechanism at the FC<->IP converter.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: July 8, 2008
    Assignee: Lucent Technologies Inc.
    Inventors: Babu Kalampukattussery Cherian, William R. Krieg, Shreedhara Maduvinakodi Ramegowda, Hemant Kumar KashinathRao Revankar, Andrew T. Schnable, Shiva Kumar Yenigalla
  • Flow control between fiber channel and wide area networks
    Publication number: 20040218531
    Abstract: Multiple fiber channel (FC) storage area networks (SANs) are interconnected over wide-area networks (WANs) to form a long-distance (e.g., greater than about 10 km) distributed storage area network (DSAN) that includes FC to Internet Protocol (IP) over WAN (e.g., SONET or gigabit Ethernet (GE)) gateways that interwork the FC buffer-to-buffer and IP/WAN flow-control mechanisms appropriate to either the SONET or GE link layers using an additive increase, multiplicative decrease (AIMD) congestion avoidance algorithm. The gateways effectively spoof the FC buffer-to-buffer credit mechanism on the FC-interface side of the gateway, while using an IP Internet control message protocol (ICMP) quench mechanism on all WAN links and additionally the IEEE 802.3 pause packet flow control mechanism on gigabit Ethernet (GE) WAN links in combination, in both cases, with a rate-throttling mechanism at the FC<->IP converter.
    Type: Application
    Filed: April 30, 2003
    Publication date: November 4, 2004
    Inventors: Babu Kalampukattussery Cherian, William R. Krieg, Shreedhara Maduvinakodi Ramegowda, Hemant Kumar KashinthRao Revankar, Andrew T. Schnable, Shiva Kumar Yenigalla