Patents by Inventor Shreekant S. Thakkar

Shreekant S. Thakkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6073210
    Abstract: The present invention discloses a method and apparatus for synchronizing weakly ordered write combining operations. A memory controller has a buffer to service memory accesses. A store fence instruction is dispatched to the memory controller. If the buffer contains at least a data written by at least one of the weakly ordered write combining operations prior to the store fence instruction, then the store fence instruction is blocked until a block in the buffer containing the data is globally observed. If the buffer does not contain any data written by at least one of the write combining operations prior to the store fence instruction, then the store fence instruction is accepted by the memory controller.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: June 6, 2000
    Assignee: Intel Corporation
    Inventors: Salvador Palanca, Vladimir Pentkovski, Subramaniam Maiyuran, Lance Hacking, Roger A. Golliver, Shreekant S. Thakkar
  • Patent number: 6014735
    Abstract: The present invention discloses a method and apparatus for encoding an instruction in an instruction set which uses a prefix code to qualify an existing opcode of an existing instruction. An opcode and an escape code are selected. The escape code is selected such that it is different from the prefix code and the existing opcode. The opcode, the escape code, and the prefix code are combined to generate an instruction code which uniquely represents the operation performed by the instruction.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: January 11, 2000
    Assignee: Intel Corporation
    Inventors: Srinivas Chennupaty, Lance Hacking, Thomas Huff, Patrice L. Roussel, Shreekant S. Thakkar
  • Patent number: 5995122
    Abstract: A method and apparatus for parallel processing of graphics data are described. A number of color components are stored in a floating point format in at least one register of a set of 128-bit registers in a packed format. The color components in the floating point format are converted to numbers in an integer format. The numbers in the integer format are placed in at least one register of a set of 64-bit registers in the packed format. Color components are assembled for image pixels from the numbers in the integer format.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: November 30, 1999
    Assignee: Intel Corporation
    Inventors: Hsien-Cheng E. Hsieh, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
  • Patent number: 5946713
    Abstract: The present invention relates to a computer system in which linear memory attributes are specified. Physical memory attributes may also be specified in physical attribute registers. A memory attribute palette (MAP) receives index signals and selects linear memory attributes in response to the index signals. An effective memory attribute selector receives selected linear memory attribute signals and, if present, the physical memory attribute signals and, in response thereto, selects effective memory attribute signals to present an effective memory attribute. In a preferred embodiment, the linear memory attributes may be programmably written into one or more registers, thereby allowing a program or OS flexibility in the choice of memory attributes, including memory attributes not currently used. The invention allows a program to apply a memory attribute of choice to a particular section of memory, thereby allowing the computer system to provide higher performance.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: August 31, 1999
    Assignee: Intel Corporation
    Inventors: Lance E. Hacking, Bryant E. Bigbee, Shahrokh Shahidzadeh, Shreekant S. Thakkar