Patents by Inventor Shreelan Savyasachi Panikkassery

Shreelan Savyasachi Panikkassery has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11140075
    Abstract: In general, the disclosure describes techniques for programming a forwarding plane of a network device to cause the forwarding plane to load balance or otherwise direct packet flows to particular central processing unit (CPU) cores among a plurality of CPU cores. For example, a network device includes a control unit comprising processing circuitry in communication with a memory, wherein the processing circuitry is configured to execute one or more processes. Additionally, the network device includes a forwarding unit comprising an interface card, a packet processor, and a forwarding unit memory. The one or more processes of the control unit are configured for execution by the processing circuitry to configure the forwarding unit memory of the forwarding unit with one or more forwarding path elements, where the one or more forwarding path elements map a packet flow to a CPU core of the plurality of CPU cores for processing.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: October 5, 2021
    Assignee: Juniper Networks, Inc.
    Inventors: Peyush Gupta, Dipankar Barman, Shreelan Savyasachi Panikkassery, Bharat Dhaker
  • Publication number: 20210288903
    Abstract: In general, the disclosure describes techniques for programming a forwarding plane of a network device to cause the forwarding plane to load balance or otherwise direct packet flows to particular central processing unit (CPU) cores among a plurality of CPU cores. For example, a network device includes a control unit comprising processing circuitry in communication with a memory, wherein the processing circuitry is configured to execute one or more processes. Additionally, the network device includes a forwarding unit comprising an interface card, a packet processor, and a forwarding unit memory. The one or more processes of the control unit are configured for execution by the processing circuitry to configure the forwarding unit memory of the forwarding unit with one or more forwarding path elements, where the one or more forwarding path elements map a packet flow to a CPU core of the plurality of CPU cores for processing.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Peyush Gupta, Dipankar Barman, Shreelan Savyasachi Panikkassery, Bharat Dhaker