Patents by Inventor Shreesh Chhabbi

Shreesh Chhabbi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10552173
    Abstract: Methods, apparatus, systems and articles of manufacture for improved margining of high-speed input-output are disclosed. An example method includes determining, in response to a system initialization, whether to perform parameter optimization for an interface. In response to the determination to perform the parameter optimization, a search is performed for parameters that optimize performance of the interface using a particle swarm optimization algorithm. The parameters that optimize the performance are applied to the interface.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: February 4, 2020
    Assignee: INTEL CORPORATION
    Inventors: Shreesh Chhabbi, Jabeena Gaibusab
  • Publication number: 20180285125
    Abstract: Methods, apparatus, systems and articles of manufacture for improved margining of high-speed input-output are disclosed. An example method includes determining, in response to a system initialization, whether to perform parameter optimization for an interface. In response to the determination to perform the parameter optimization, a search is performed for parameters that optimize performance of the interface using a particle swarm optimization algorithm. The parameters that optimize the performance are applied to the interface.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: SHREESH CHHABBI, JABEENA GAIBUSAB
  • Patent number: 9817054
    Abstract: Methods and apparatus relating to electrical margining of multi-parameter high-speed interconnect links with multi-sample probing are described. In one embodiment, logic is provided to generate one or more parameter values, corresponding to an electrical operating margin of an interconnect. The one or more parameter values are generated based on a plurality of eye observation sets to be detected in response to operation of the interconnect in accordance with a plurality of parameter sets (e.g., by using quantitative optimization techniques). In turn, the interconnect is to be operated at the one or more parameter values if it is determined that the one or more parameter values cause the interconnect to operate at an optimum level relative to an operation of the interconnect in accordance with one or more less optimum parameter levels. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 14, 2017
    Assignee: Intel Corporation
    Inventors: Thanunathan Rangarajan, Shreesh Chhabbi, Arvind A. Kumar, Venkatraman Iyer
  • Publication number: 20140002102
    Abstract: Methods and apparatus relating to electrical margining of multi-parameter high-speed interconnect links with multi-sample probing are described. In one embodiment, logic is provided to generate one or more parameter values, corresponding to an electrical operating margin of an interconnect. The one or more parameter values are generated based on a plurality of eye observation sets to be detected in response to operation of the interconnect in accordance with a plurality of parameter sets (e.g., by using quantitative optimization techniques). In turn, the interconnect is to be operated at the one or more parameter values if it is determined that the one or more parameter values cause the interconnect to operate at an optimum level relative to an operation of the interconnect in accordance with one or more less optimum parameter levels. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 28, 2012
    Publication date: January 2, 2014
    Inventors: Thanunathan Rangarajan, Shreesh Chhabbi, Arvind A. Kumar, Venkatraman Iyer