Patents by Inventor Shreesh Narasimha

Shreesh Narasimha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • GERMANIUM OXIDE FREE ATOMIC LAYER DEPOSITION OF SILICON OXIDE AND HIGH-K GATE DIELECTRIC ON GERMANIUM CONTAINING CHANNEL FOR CMOS DEVICES
    Publication number: 20130126986
    Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 23, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: MaryJane Brodsky, Murshed M. Chowdhury, Michael P. Chudzik, Min Dai, Siddarth A. Krishnan, Shreesh Narasimha, Shahab Siddiqui
  • Threshold Voltage Adjustment For Thin Body Mosfets
    Publication number: 20130105896
    Abstract: A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor.
    Type: Application
    Filed: September 24, 2012
    Publication date: May 2, 2013
    Applicant: International Business Machines Corporation
    Inventors: MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Shreesh Narasimha, Yue Liang, Liyang Song, Yanfeng Wang, Chun-Chen Yeh
  • THRESHOLD VOLTAGE ADJUSTMENT FOR THIN BODY MOSFETS
    Publication number: 20130105894
    Abstract: A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.
    Type: Application
    Filed: October 27, 2011
    Publication date: May 2, 2013
    Applicant: International Business Machines Corporation
    Inventors: MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Shreesh Narasimha, Yue Liang, Liyang Song, Yanfeng Wang, Chun-Chen Yeh
  • SHALLOW TRENCH ISOLATION STRUCTURE HAVING A NITRIDE PLUG
    Publication number: 20130093040
    Abstract: A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates.
    Type: Application
    Filed: October 18, 2011
    Publication date: April 18, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Byeong Y. Kim, Shreesh Narasimha
  • Work Function Adjustment By Carbon Implant In Semiconductor Devices Including Gate Structure
    Publication number: 20130087859
    Abstract: A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.
    Type: Application
    Filed: October 5, 2011
    Publication date: April 11, 2013
    Applicant: International Business Machines Corporation
    Inventors: Yue Liang, Dechao Guo, William K. Henson, Shreesh Narasimha, Yanfeng Wang
  • Reducing dislocation formation in semiconductor devices through targeted carbon implantation
    Patent number: 8343825
    Abstract: A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: January 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Anthony G. Domenicucci, Shreesh Narasimha, Karen A. Nummy, Viorel C. Ontalus, Yun-Yu Wang
  • Electrical mask inspection
    Patent number: 8343781
    Abstract: An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: January 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Arvind Kumar, Anthony I-Chih Chou, Shreesh Narasimha
  • Nanowire Field Effect Transistors
    Publication number: 20120329217
    Abstract: A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer.
    Type: Application
    Filed: August 31, 2012
    Publication date: December 27, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Shreesh Narasimha, Jeffrey W. Sleight
  • PLANAR AND NANOWIRE FIELD EFFECT TRANSISTORS
    Publication number: 20120319084
    Abstract: An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer.
    Type: Application
    Filed: August 31, 2012
    Publication date: December 20, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Shreesh Narasimha, Jeffrey W. Sleight
  • Contacts for Nanowire Field Effect Transistors
    Publication number: 20120280205
    Abstract: A nanowire field effect transistor (FET) device includes a channel region including a silicon nanowire portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate stack disposed circumferentially around the silicon portion, a source region including the first distal end of the silicon nanowire portion, a drain region including the second distal end of the silicon nanowire portion, a metallic layer disposed on the source region and the drain region, a first conductive member contacting the metallic layer of the source region, and a second conductive member contacting the metallic layer of the drain region.
    Type: Application
    Filed: July 18, 2012
    Publication date: November 8, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Shreesh Narasimha, Jeffrey W. Sleight
  • Compact model methodology for PC landing pad lithographic rounding impact on device performance
    Patent number: 8302040
    Abstract: A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Gerald M. Davidson, Paul A. Hyde, Judith H. McCullen, Shreesh Narasimha
  • Methodology for improving device performance prediction from effects of active area corner rounding
    Patent number: 8296691
    Abstract: A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: October 23, 2012
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Gerald M. Davidson, Paul A. Hyde, Judith H. McCullen, Shreesh Narasimha
  • Method of fabricating a device using low temperature anneal processes, a device and design structure
    Patent number: 8236709
    Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Anthony G. Domenicucci, Terence L. Kane, Shreesh Narasimha, Karen A. Nummy, Viorel Ontalus, Yun-Yu Wang
  • Bulk substrate FET integrated on CMOS SOI
    Patent number: 8232599
    Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Ning Su, Huiling Shang
  • Gated diode structure and method including relaxed liner
    Patent number: 8232603
    Abstract: A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Anthony I. Chou, Gregory G. Freeman, Kevin McStay, Shreesh Narasimha
  • BULK SUBSTRATE FET INTEGRATED ON CMOS SOI
    Publication number: 20120187492
    Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
    Type: Application
    Filed: March 21, 2012
    Publication date: July 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Ning Su, Huiling Shang
  • REDUCING DISLOCATION FORMATION IN SEMICONDUCTOR DEVICES THROUGH TARGETED CARBON IMPLANTATION
    Publication number: 20120184075
    Abstract: A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.
    Type: Application
    Filed: January 19, 2011
    Publication date: July 19, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony G. Domenicucci, Shreesh Narasimha, Karen A. Nummy, Viorel C. Ontalus, Yun-Yu Wang
  • METHOD OF FABRICATING A DEVICE USING LOW TEMPERATURE ANNEAL PROCESSES, A DEVICE AND DESIGN STRUCTURE
    Publication number: 20120180010
    Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.
    Type: Application
    Filed: March 15, 2012
    Publication date: July 12, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony G. DOMENICUCCI, Terence L. Kane, Shreesh Narasimha, Karen A. Nummy, Viorel Ontalus, Yun-Yu Wang
  • BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION
    Publication number: 20120112280
    Abstract: A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
    Type: Application
    Filed: November 10, 2010
    Publication date: May 10, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey B. Johnson, Shreesh Narasimha, Hasan M. Nayfeh, Viorel Ontalus, Robert R. Robison
  • Nanowire Field Effect Transistors
    Publication number: 20120068150
    Abstract: A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 22, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Shreesh Narasimha, Jeffrey W. Sleight