Patents by Inventor Shreesha Prabhu

Shreesha Prabhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240053916
    Abstract: Methods, systems, and devices for resuming write operation after suspension are described. A memory system may be configured to determine an upper limit of a threshold voltage of a page of a block at which a performance of a write operation was suspended based at least in part on an indication to resume the performance of the write operation that was previously suspended at a memory system; determine a difference between a first quantity of a first logic state stored in the page and a second quantity of the first logic state associated with an unsuspended write operation based at least in part on determining the upper limit of the threshold voltage; and resume the performance of the write operation based at least in part on determining the difference between the first quantity of the first logic state and the second quantity of the first logic state.
    Type: Application
    Filed: August 9, 2022
    Publication date: February 15, 2024
    Inventors: Amiya Banerjee, Kranthi Kumar Vaidyula, Shreesha Prabhu
  • Patent number: 10892025
    Abstract: A non-volatile storage apparatus includes a plurality of non-volatile memory cells and control circuitry. The control circuitry is configured to apply one or more soft erase pulses to the plurality of non-volatile memory cells to reduce threshold voltages of the plurality of non-volatile memory cells from initial levels corresponding to programmed data to intermediate levels below the initial levels and above an erased level. The control circuitry is configured to apply one or more soft programming pulse to increase threshold voltages of the plurality of non-volatile memory cells from the intermediate levels to final levels corresponding to the programmed data.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: January 12, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amiya Banerjee, Shreesha Prabhu, Saugata Das Purkayastha
  • Publication number: 20200395087
    Abstract: A non-volatile storage apparatus includes a plurality of non-volatile memory cells and control circuitry. The control circuitry is configured to apply one or more soft erase pulses to the plurality of non-volatile memory cells to reduce threshold voltages of the plurality of non-volatile memory cells from initial levels corresponding to programmed data to intermediate levels below the initial levels and above an erased level. The control circuitry is configured to apply one or more soft programming pulse to increase threshold voltages of the plurality of non-volatile memory cells from the intermediate levels to final levels corresponding to the programmed data.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 17, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amiya Banerjee, Shreesha Prabhu, Saugata Das Purkayastha