Patents by Inventor Shrestha GANGULY

Shrestha GANGULY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11437307
    Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: September 6, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Abdolreza Langari, Yuan Li, Shrestha Ganguly, Terence Cheung, Ching-Liou Huang, Hui Wang
  • Publication number: 20210066177
    Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.
    Type: Application
    Filed: November 11, 2020
    Publication date: March 4, 2021
    Inventors: Abdolreza LANGARI, Yuan LI, Shrestha GANGULY, Terence CHEUNG, Ching-Liou HUANG, Hui WANG
  • Patent number: 10916494
    Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: February 9, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Abdolreza Langari, Yuan Li, Shrestha Ganguly, Terence Cheung, Ching-Liou Huang, Hui Wang
  • Publication number: 20200211943
    Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.
    Type: Application
    Filed: June 26, 2019
    Publication date: July 2, 2020
    Inventors: Abdolreza LANGARI, Yuan LI, Shrestha GANGULY, Terence CHEUNG, Ching-Liou HUANG, Hui WANG