Patents by Inventor Shreyas Kher

Shreyas Kher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8343279
    Abstract: Embodiments of the invention provide apparatuses and methods for depositing materials on substrates during vapor deposition processes, such as atomic layer deposition (ALD). In one embodiment, a chamber contains a substrate support with a receiving surface and a chamber lid containing an expanding channel formed within a thermally insulating material. The chamber further includes at least one conduit coupled to a gas inlet within the expanding channel and positioned to provide a gas flow through the expanding channel in a circular direction, such as a vortex, a helix, a spiral or derivatives thereof. The expanding channel may be formed directly within the chamber lid or formed within a funnel liner attached thereon. The chamber may contain a retaining ring, an upper process liner, a lower process liner or a slip valve liner. Liners usually have a polished surface finish and contain a thermally insulating material such as fused quartz or ceramic.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: January 1, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Nyi Oo Myo, Kenric Choi, Shreyas Kher, Pravin Narwankar, Steve Poppe, Craig R. Metzner, Paul Deaten
  • Patent number: 8282992
    Abstract: Embodiments of the invention provide methods for depositing materials on substrates during vapor deposition processes, such as atomic layer deposition (ALD). In one embodiment, a chamber contains a substrate support with a receiving surface and a chamber lid containing an expanding channel formed within a thermally insulating material. The chamber further includes at least one conduit coupled to a gas inlet within the expanding channel and positioned to provide a gas flow through the expanding channel in a circular direction, such as a vortex, a helix, a spiral, or derivatives thereof. The expanding channel may be formed directly within the chamber lid or formed within a funnel liner attached thereon. The chamber may contain a retaining ring, an upper process liner, a lower process liner or a slip valve liner. Liners usually have a polished surface finish and contain a thermally insulating material such as fused quartz or ceramic.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: October 9, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Nyi Oo Myo, Kenric Cho, Shreyas Kher, Pravin Narwankar, Steve Poppe, Craig R. Metzner, Paul Deaten
  • Patent number: 7910446
    Abstract: Electronic devices and methods for forming electronic devices that allow for a reduction in device dimensions while also maintaining or reducing leakage current for non-volatile memory devices are provided. In one embodiment, a method of fabricating a non-volatile memory device is provided. The method comprises depositing a floating gate polysilicon layer on a substrate, forming a silicon oxide layer on the floating gate polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a high-k dielectric material layer on the first silicon oxynitride layer, depositing a second silicon oxynitride on the high-k dielectric material, and forming a control gate polysilicon layer on the second silicon oxynitride layer. In one embodiment, the high-k dielectric material layer comprises hafnium silicon oxynitride.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: March 22, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Yi Ma, Shreyas Kher, Khaled Ahmed
  • Patent number: 7816200
    Abstract: The present invention generally includes a method and an apparatus for depositing both a high k layer and a capping layer within the same processing chamber by coupling gas precursors, liquid precursors, and solid precursors to the same processing chamber. By coupling gas precursors, liquid precursors, and solid precursors to the same processing chamber, a high k dielectric layer, a capping layer for a PMOS section, and a different capping layer for a NMOS may be deposited within the same processing chamber. The capping layer prevents the metal containing electrode from reacting with the high k dielectric layer. Thus, the threshold voltage for the PMOS and NMOS may be substantially identical.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: October 19, 2010
    Assignee: Applied Materials, Inc.
    Inventor: Shreyas Kher
  • Patent number: 7794544
    Abstract: The embodiments of the invention describe a process chamber, such as an ALD chamber, that has gas delivery conduits with gradually increasing diameters to reduce Joule-Thompson effect during gas delivery, a ring-shaped gas liner leveled with the substrate support to sustain gas temperature and to reduce gas flow to the substrate support backside, and a gas reservoir to allow controlled delivery of process gas. The gas conduits with gradually increasing diameters, the ring-shaped gas liner, and the gas reservoir help keep the gas temperature stable and reduce the creation of particles.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: September 14, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Son T. Nguyen, Kedarnath Sangam, Miriam Schwartz, Kenric Choi, Sanjay Bhat, Pravin K. Narwankar, Shreyas Kher, Rahul Sharangapani, Shankar Muthukrishnan, Paul Deaton
  • Publication number: 20090263961
    Abstract: The present invention generally includes a method and an apparatus for depositing both a high k layer and a capping layer within the same processing chamber by coupling gas precursors, liquid precursors, and solid precursors to the same processing chamber. By coupling gas precursors, liquid precursors, and solid precursors to the same processing chamber, a high k dielectric layer, a capping layer for a PMOS section, and a different capping layer for a NMOS may be deposited within the same processing chamber. The capping layer prevents the metal containing electrode from reacting with the high k dielectric layer. Thus, the threshold voltage for the PMOS and NMOS may be substantially identical.
    Type: Application
    Filed: April 22, 2008
    Publication date: October 22, 2009
    Inventor: SHREYAS KHER
  • Patent number: 7601648
    Abstract: Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 ? utilized as a gate dielectric layer in a gate structure.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: October 13, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Thai Cheng Chua, Shankar Muthukrisnan, Johanes Swenberg, Shreyas Kher, Chikuang Charles Wang, Giuseppina Conti, Yuri Uritsky
  • Patent number: 7547952
    Abstract: The present invention generally is a method for forming a high-k dielectric layer, comprising depositing a hafnium compound by atomic layer deposition to a substrate, comprising, delivering a hafnium precursor to a surface of the substrate, reacting the hafnium precursor and forming a hafnium containing layer to the surface, delivering a nitrogen precursor to the hafnium containing layer, forming at least one hafnium nitrogen bond and depositing the hafnium compound to the surface.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: June 16, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Craig Metzner, Shreyas Kher, Yeong Kwan Kim, M. Noel Rocklein, Steven M. George
  • Publication number: 20090020802
    Abstract: Electronic devices and methods for forming electronic devices that allow for a reduction in device dimensions while also maintaining or reducing leakage current for non-volatile memory devices are provided. In one embodiment, a method of fabricating a non-volatile memory device is provided. The method comprises depositing a floating gate polysilicon layer on a substrate, forming a silicon oxide layer on the floating gate polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a high-k dielectric material layer on the first silicon oxynitride layer, depositing a second silicon oxynitride on the high-k dielectric material, and forming a control gate polysilicon layer on the second silicon oxynitride layer. In one embodiment, the high-k dielectric material layer comprises hafnium silicon oxynitride.
    Type: Application
    Filed: June 27, 2008
    Publication date: January 22, 2009
    Inventors: YI MA, SHREYAS KHER, KHALED AHMED
  • Publication number: 20080268154
    Abstract: Methods for forming a high-k dielectric layer that may be utilized to form a metal gate structure in TANOS charge trap flash memories. In one embodiment, the method may include providing a substrate into a chamber, supplying a gas mixture containing an oxygen containing gas and aluminum containing compound into the chamber, wherein the aluminum containing compound has a formula selected from a group consisting of RxAly(OR?)x and Al(NRR?)3, heating the substrate, and depositing an aluminum oxide layer having a dielectric constant greater than 8 on the heated substrate by a chemical vapor deposition process.
    Type: Application
    Filed: April 30, 2007
    Publication date: October 30, 2008
    Inventors: SHREYAS KHER, Tejal Goyani, Balaji Kannan
  • Publication number: 20080063798
    Abstract: The present invention generally comprises an apparatus for depositing high k dielectric or metal gate materials in which toxic, flammable, or pyrophoric precursors may be used. Exhaust conduits may be placed on the liquid precursor or solid precursor delivery cabinet, the gas panel, and the water vapor generator area. The exhaust conduits permit a technician to access the apparatus without undue exposure to toxic, pyrophoric, or flammable gases that may collect within the liquid deliver cabinet, gas panel, and water vapor generator area.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 13, 2008
    Inventors: Shreyas Kher, Son Nguyen, Pravin Narwankar, Sanjeev Tandon, Steve Jumper, Vincent Sermona
  • Publication number: 20080057737
    Abstract: A method of forming a dielectric stack on a pre-treated surface. The method comprises pre-cleaning a semiconductor wafer to remove native oxide, such as by applying hydrofluoric acid to form an HF-last surface, pre-treating the HF-last surface with ozonated deionized water, forming a dielectric stack on the pre-treated surface and providing a flow of NH3 in a process zone surrounding the wafer. Alternately, the method includes pre-treating the HF-last surface with NH3, forming the stack after the pre-treating, and providing a flow of N2 in a process zone surrounding the wafer after the forming. The method also includes pre-treating the HF-last surface using an in-situ steam generation process, forming the stack on the pre-treated surface, and annealing the wafer after the forming.
    Type: Application
    Filed: October 30, 2007
    Publication date: March 6, 2008
    Inventors: CRAIG METZNER, Shreyas Kher, Shixue Han
  • Publication number: 20080041307
    Abstract: The embodiments of the invention describe a process chamber, such as an ALD chamber, that has gas delivery conduits with gradually increasing diameters to reduce Joule-Thompson effect during gas delivery, a ring-shaped gas liner leveled with the substrate support to sustain gas temperature and to reduce gas flow to the substrate support backside, and a gas reservoir to allow controlled delivery of process gas. The gas conduits with gradually increasing diameters, the ring-shaped gas liner, and the gas reservoir help keep the gas temperature stable and reduce the creation of particles.
    Type: Application
    Filed: October 26, 2007
    Publication date: February 21, 2008
    Inventors: Son Nguyen, Kedarnath Sangam, Miriam Schwartz, Kenric Choi, Sanjay Bhat, Pravin Narwankar, Shreyas Kher, Rahul Sharangapani, Shankar Muthukrishnam, Paul Deaton
  • Publication number: 20080044569
    Abstract: Embodiments of the invention provide methods for depositing materials on substrates during vapor deposition processes, such as atomic layer deposition (ALD). In one embodiment, a chamber contains a substrate support with a receiving surface and a chamber lid containing an expanding channel formed within a thermally insulating material. The chamber further includes at least one conduit coupled to a gas inlet within the expanding channel and positioned to provide a gas flow through the expanding channel in a circular direction, such as a vortex, a helix, a spiral, or derivatives thereof. The expanding channel may be formed directly within the chamber lid or formed within a funnel liner attached thereon. The chamber may contain a retaining ring, an upper process liner, a lower process liner or a slip valve liner. Liners usually have a polished surface finish and contain a thermally insulating material such as fused quartz or ceramic.
    Type: Application
    Filed: October 26, 2007
    Publication date: February 21, 2008
    Inventors: Nyi Myo, Kenric Cho, Shreyas Kher, Pravin Narwankar, Steve Poppe, Craig Metzner, Paul Deaten
  • Publication number: 20080026553
    Abstract: Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 ? utilized as a gate dielectric layer in a gate structure.
    Type: Application
    Filed: July 31, 2006
    Publication date: January 31, 2008
    Inventors: Thai Cheng Chua, Shankar Muthukrisnan, Johanes Swenberg, Shreyas Kher, Chikuang Charles Wang, Giuseppina Conti, Yuri Uritsky
  • Publication number: 20070059948
    Abstract: Embodiments of the invention provide methods for forming hafnium materials, such as oxides and nitrides, by sequentially exposing a substrate to hafnium precursors and active oxygen or nitrogen species (e.g., ozone, oxygen radicals, or nitrogen radicals). The deposited hafnium materials have significantly improved uniformity when deposited by these atomic layer deposition (ALD) processes. In one embodiment, an ALD chamber contains an expanding channel having a bottom surface that is sized and shaped to substantially cover a substrate positioned on a substrate pedestal. During an ALD process for forming hafnium materials, process gases form a vortex flow pattern while passing through the expanding channel and sweep across the substrate surface. The substrate is sequentially exposed to chemical precursors that are pulsed into the process chamber having the vortex flow.
    Type: Application
    Filed: May 31, 2006
    Publication date: March 15, 2007
    Inventors: Craig Metzner, Shreyas Kher, Vidyut Gopal, Shixue Han, Shankarram Athreya
  • Publication number: 20070049043
    Abstract: A method and apparatus for forming a nitrided gate dielectric. The method comprises incorporating nitrogen into a dielectric film using a plasma nitridation process to form a nitrided gate dielectric. The first step involves providing a substrate comprising a gate dielectric film. The second step involves inducing a voltage on the substrate. Finally, the substrate is exposed to a plasma comprising a nitrogen source while maintaining the voltage to form a nitrided gate dielectric on the substrate. In one embodiment, the voltage is induced on the substrate by applying a voltage to an electrostatic chuck supporting the substrate. In another embodiment, the voltage is induced on the substrate by applying a DC bias voltage to an electrode positioned adjacent the substrate.
    Type: Application
    Filed: August 23, 2005
    Publication date: March 1, 2007
    Inventors: Shankar Muthukrishnan, Rahul Sharangpani, Tejal Goyani, Pravin Narwankar, Shreyas Kher, Yi Ma, Giuseppina Conti
  • Publication number: 20060264067
    Abstract: Embodiments of the present invention relate to a surface preparation treatment for the formation of thin films of high k dielectric materials over substrates. One embodiment of a method of forming a high k dielectric layer over a substrate includes pre-cleaning a surface of a substrate to remove native oxides, pre-treating the surface of the substrate with a hydroxylating agent, and forming a high k dielectric layer over the surface of the substrate. One embodiment of a method of forming a hafnium containing layer over a substrate includes introducing an acid solution to a surface of a substrate, introducing a hydrogen containing gas and an oxygen containing gas to the surface of the substrate, and forming a hafnium containing layer over the substrate.
    Type: Application
    Filed: July 6, 2006
    Publication date: November 23, 2006
    Inventors: Shreyas Kher, Shixue Han, Craig Metzner
  • Publication number: 20060223339
    Abstract: Methods of forming metal compounds such as metal oxides or metal nitrides by sequentially introducing and then reacting metal organic compounds with ozone one or with oxygen radicals or nitrogen radicals formed in a remote plasma chamber. The metal compounds have surprisingly and significantly improved uniformity when deposited by atomic layer deposition with cycle times of at least 10 seconds. The metal compounds also do not contain detectable carbon when the metal organic compound is vaporized at process conditions in the absence of solvents or excess ligands.
    Type: Application
    Filed: May 31, 2006
    Publication date: October 5, 2006
    Inventors: Craig Metzner, Shreyas Kher, Vidyut Gopal, Shixue Han, Shankarram Athreya
  • Publication number: 20060208215
    Abstract: The present invention generally is a method for forming a high-k dielectric layer, comprising depositing a hafnium compound by atomic layer deposition to a substrate, comprising, delivering a hafnium precursor to a surface of the substrate, reacting the hafnium precursor and forming a hafnium containing layer to the surface, delivering a nitrogen precursor to the hafnium containing layer, forming at least one hafnium nitrogen bond and depositing the hafnium compound to the surface.
    Type: Application
    Filed: May 30, 2006
    Publication date: September 21, 2006
    Inventors: Craig Metzner, Shreyas Kher, Yeong Kim, M. Rocklein, Steven George