Patents by Inventor Shreyas Sundaram

Shreyas Sundaram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiply execution unit for performing integer and XOR multiplication
    Patent number: 7139787
    Abstract: A multiply execution unit that is operable to generate the integer product and the XOR product of a multiplicand and a multiplier. The multiply execution unit includes a summing circuit for summing a plurality of partial products. The partial products may be Booth encoded. The summing circuit can generate an integer sum of the plurality of partial products and can generate an XOR sum of the plurality of partial products. The summing circuit includes a first plurality of full adders. The first plurality of full adders each has three inputs, a carry output, and a sum output. The sum outputs of the first plurality of full adders are independent of the value of any carry output in the summing circuit. The summing circuit also includes a second plurality of full adders. The second plurality of full adders each has three inputs, a carry output, and a sum output.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: November 21, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Leonard D. Rarick, Sheueling Chang Shantz, Shreyas Sundaram
  • Multiply execution unit for preforming integer and XOR multiplication
    Publication number: 20040153489
    Abstract: A multiply execution unit that is operable to generate the integer product and the XOR product of a multiplicand and a multiplier. The multiply execution unit includes a summing circuit for summing a plurality of partial products. The partial products may be Booth encoded. The summing circuit can generate an integer sum of the plurality of partial products and can generate an XOR sum of the plurality of partial products. The summing circuit includes a first plurality of full adders. The first plurality of full adders each has three inputs, a carry output, and a sum output. The sum outputs of the first plurality of full adders are independent of the value of any carry output in the summing circuit. The summing circuit also includes a second plurality of full adders. The second plurality of full adders each has three inputs, a carry output, and a sum output.
    Type: Application
    Filed: January 30, 2003
    Publication date: August 5, 2004
    Inventors: Leonard D. Rarick, Sheueling Chang Shantz, Shreyas Sundaram