Abstract: A method for performing automated detection of transaction latency for a processor design model running an application in a hardware simulation accelerator. The method includes loading the processor design model into the hardware simulation accelerator, loading the application into the processor design model running within the hardware simulation accelerator, simulating the processor design model running the application within the hardware simulation accelerator, and for each individual transaction of the application: establishing a first checkpoint at a start of an execution of the individual transaction by creating a breakpoint and resetting a counter, establishing a second checkpoint at a completion of the transaction by creating another breakpoint and obtaining latency information for the second checkpoint. The latencies of the individual transaction from the start to the completion are measured based on the latency information.

Abstract: A neural network in multi-task deep learning paradigm for machine vision includes an encoder that further includes a first, a second, and a third tier. The first tier comprises a first-tier unit having one or more first-unit blocks. The second tier receives a first-tier output from the first tier at one or more second-tier units in the second tier, a second-tier unit comprises one or more second-tier blocks, the third tier receives a second-tier output from the second tier at one or more third-tier units in the third tier, and a third-tier block comprises one or more third-tier blocks. The neural network further comprises a decoder operatively the encoder to receive an encoder output from the encoder as well as one or more loss function layers that are configured to backpropagate one or more losses for training at least the encoder of the neural network in a deep learning paradigm.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for training an object recognition neural network using multiple data sources. One of the methods includes receiving training data that includes a plurality of training images from a first source and images from a second source. A set of training images are obtained from the training data. For each training image in the set of training images, contrast equalization is applied to the training image to generate a modified image. The modified image is processed using the neural network to generate an object recognition output for the modified image. A loss is determined based on errors between, for each training image in the set, the object recognition output for the modified image generated from the training image and ground-truth annotation for the training image. Parameters of the neural network are updated based on the determined loss.

Abstract: A method of performing instruction marking in a computer processor architecture includes fetching instructions from a memory unit by a fetching unit in the computer processor architecture. Instruction groups for marking are determined. Fetched instructions are matched to instruction groups for marking. The fetched instructions are marked. Some of the marked instructions are selectively unmarked. The marked and unmarked instructions are forwarded to a queue of instructions for processing in the computer processor architecture.

Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for detecting deviations from targeted design performance in accelerator/emulator environment. In an embodiment, the method comprises loading target vales for a performance metric onto a hardware-accelerated simulator; setting breakpoints to pause the simulator at defined intervals; simulating, by the hardware-accelerated simulator, execution of a circuit design. The method further comprises during the simulating, using said breakpoints to pause the simulating at the defined intervals, and during each pause, comparing a measured value for the performance metric to the target value for the performance metric; and ending the simulation when a specified condition based on said comparing is met. In embodiments, when a difference between the measured value for the performance metric and the target value for the performance metric is within a preset tolerance, the pause is ended and the simulation continues.

Abstract: A method, system and computer program product are disclosed for reducing the memory load time for logic simulator. In an embodiment, the method comprises identifying a memory for a program, and selectively loading onto a logic simulator parts of the memory that are pre-determined as parts of the memory that will be accessed by the program when the program is executed on the simulator. In an embodiment, the selectively loading onto a logic simulator parts of the memory includes pre-determining subsets of the memory that will be accessed by the program when the program is executed on the simulator, and loading the pre-determined subsets of the memory on the simulator. In an embodiment, the pre-determining subsets of the memory includes using addresses of the memory that are accessed by the program when the program is executed on a computer system, to create the pre-determined subsets of the memory.

Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for detecting deviations from targeted design performance in accelerator/emulator environment. In an embodiment, the method comprises loading target vales for a performance metric onto a hardware-accelerated simulator; setting breakpoints to pause the simulator at defined intervals; simulating, by the hardware-accelerated simulator, execution of a circuit design. The method further comprises during the simulating, using said breakpoints to pause the simulating at the defined intervals, and during each pause, comparing a measured value for the performance metric to the target value for the performance metric; and ending the simulation when a specified condition based on said comparing is met. In embodiments, when a difference between the measured value for the performance metric and the target value for the performance metric is within a preset tolerance, the pause is ended and the simulation continues.

Abstract: A method for performing automated detection of transaction latency for a processor design model running an application in a hardware simulation accelerator. The method includes loading the processor design model into the hardware simulation accelerator, loading the application into the processor design model running within the hardware simulation accelerator, simulating the processor design model running the application within the hardware simulation accelerator, and for each individual transaction of the application: establishing a first checkpoint at a start of an execution of the individual transaction by creating a breakpoint and resetting a counter, establishing a second checkpoint at a completion of the transaction by creating another breakpoint and obtaining latency information for the second checkpoint. The latencies of the individual transaction from the start to the completion are measured based on the latency information.

Abstract: A method, system and computer program product are disclosed for reducing the memory load time for logic simulator. In an embodiment, the method comprises identifying a memory for a program, and selectively loading onto a logic simulator parts of the memory that are pre-determined as parts of the memory that will be accessed by the program when the program is executed on the simulator. In an embodiment, the selectively loading onto a logic simulator parts of the memory includes pre-determining subsets of the memory that will be accessed by the program when the program is executed on the simulator, and loading the pre-determined subsets of the memory on the simulator. In an embodiment, the pre-determining subsets of the memory includes using addresses of the memory that are accessed by the program when the program is executed on a computer system, to create the pre-determined subsets of the memory.

Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes generating workload information of a performance base test; determining characteristics of the workload information; determining one or more constraints that can cause behavioral changes to a design of the processor; combining the determined characteristics and the determined one or more constraints to generate one or more example constraints; testing the one or more example constraints in one or more example performance tests; and generating one or more performance benchmarks for the performance base test and the one or more example performance tests.

Abstract: A neural network in multi-task deep learning paradigm for machine vision includes an encoder that further includes a first, a second, and a third tier. The first tier comprises a first-tier unit having one or more first-unit blocks. The second tier receives a first-tier output from the first tier at one or more second-tier units in the second tier, a second-tier unit comprises one or more second-tier blocks, the third tier receives a second-tier output from the second tier at one or more third-tier units in the third tier, and a third-tier block comprises one or more third-tier blocks. The neural network further comprises a decoder operatively the encoder to receive an encoder output from the encoder as well as one or more loss function layers that are configured to backpropagate one or more losses for training at least the encoder of the neural network in a deep learning paradigm.

Abstract: Examples of techniques for software translation prefetch instructions are described herein. An aspect includes, based on encountering a translation prefetch instruction in software that is being executed by a processor, determining whether an address translation corresponding to the translation prefetch instruction is located in a translation lookaside buffer (TLB) of the processor. Another aspect includes, based on determining that the address translation is not located in the TLB, issuing an address translation request corresponding to the translation prefetch instruction. Another aspect includes storing an address translation corresponding to the address translation request in the TLB.

Abstract: Examples of techniques for software translation prefetch instructions are described herein. An aspect includes, based on encountering a translation prefetch instruction in software that is being executed by a processor, determining whether an address translation corresponding to the translation prefetch instruction is located in a translation lookaside buffer (TLB) of the processor. Another aspect includes, based on determining that the address translation is not located in the TLB, issuing an address translation request corresponding to the translation prefetch instruction. Another aspect includes storing an address translation corresponding to the address translation request in the TLB.

Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes generating workload information of a performance base test; determining characteristics of the workload information; determining one or more constraints that can cause behavioral changes to a design of the processor; combining the determined characteristics and the determined one or more constraints to generate one or more example constraints; testing the one or more example constraints in one or more example performance tests; and generating one or more performance benchmarks for the performance base test and the one or more example performance tests.

Abstract: A method is disclosed of providing a providing a content discovery platform for optimizing social network engagements. The method is implemented in one or more servers programmed to execute the method. The method comprising retrieving social media data from registered users on one or more social networks, wherein the social media data includes one or more URLs associated with one or more articles, respectively, computing a social importance score for each URL of the one or more URLs, and ranking the one or more URLs by social importance score.

Abstract: A method is disclosed of providing a providing a content discovery platform for optimizing social network engagements. The method is implemented in one or more servers programmed to execute the method. The method comprising retrieving social media data from registered users on one or more social networks, wherein the social media data includes one or more URLs associated with one or more articles, respectively, computing a social importance score for each URL of the one or more URLs, and ranking the one or more URLs by social importance score.

Abstract: The system relates to a system and apparatus for a scalable engineering system deployed in production that mines topical interests from multiple social networks and assigns over tens of thousands of topics to hundreds of millions of users on a daily basis. The system extracts and analyzes features for topic inference that extend beyond authored text. The system uses a diverse set of features and cross network information can lead to a better understanding of a user's interests. This system focuses on assigning topics for a user that other users can socially recognize and acknowledge.

Abstract: The techniques, methods and systems described herein facilitate the automated discovery and presentation of content created, published or otherwise made public by “experts” and key influencers on particular topics. As such, users that may be interested in particular topics but may not know who to connect with in order to receive the most pertinent information can receive highly-relevant information. Embodiments of the invention use topics of interest identified by the user and/or automatically identifies topics based on previous postings, communication, contacts, etc. Individuals, companies, organizations and other entities that have been recognized as highly influential in those topics are identified and, without explicit actions by the user, adds content generated by the influential entities to the user's content data feed.

Abstract: The techniques, methods and systems described herein facilitate the automated discovery and presentation of content created, published or otherwise made public by “experts” and key influencers on particular topics. As such, users that may be interested in particular topics but may not know who to connect with in order to receive the most pertinent information can receive highly-relevant information. Embodiments of the invention use topics of interest identified by the user and/or automatically identifies topics based on previous postings, communication, contacts, etc. Individuals, companies, organizations and other entities that have been recognized as highly influential in those topics are identified and, without explicit actions by the user, adds content generated by the influential entities to the user's content data feed.