Patents by Inventor Shricharan Srivatsan
Shricharan Srivatsan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11875095Abstract: A method for performing automated detection of transaction latency for a processor design model running an application in a hardware simulation accelerator. The method includes loading the processor design model into the hardware simulation accelerator, loading the application into the processor design model running within the hardware simulation accelerator, simulating the processor design model running the application within the hardware simulation accelerator, and for each individual transaction of the application: establishing a first checkpoint at a start of an execution of the individual transaction by creating a breakpoint and resetting a counter, establishing a second checkpoint at a completion of the transaction by creating another breakpoint and obtaining latency information for the second checkpoint. The latencies of the individual transaction from the start to the completion are measured based on the latency information.Type: GrantFiled: July 1, 2020Date of Patent: January 16, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John A. Schumann, Tharunachalam Pindicura, Shricharan Srivatsan, Vivek Britto, Madhumitha Venkataraman
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Publication number: 20230048717Abstract: A method of performing instruction marking in a computer processor architecture includes fetching instructions from a memory unit by a fetching unit in the computer processor architecture. Instruction groups for marking are determined. Fetched instructions are matched to instruction groups for marking. The fetched instructions are marked. Some of the marked instructions are selectively unmarked. The marked and unmarked instructions are forwarded to a queue of instructions for processing in the computer processor architecture.Type: ApplicationFiled: August 4, 2021Publication date: February 16, 2023Inventors: Shricharan Srivatsan, John A. Schumann, Wallace Keith Sharp, Gregory A. Kemp
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Patent number: 11562116Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for detecting deviations from targeted design performance in accelerator/emulator environment. In an embodiment, the method comprises loading target vales for a performance metric onto a hardware-accelerated simulator; setting breakpoints to pause the simulator at defined intervals; simulating, by the hardware-accelerated simulator, execution of a circuit design. The method further comprises during the simulating, using said breakpoints to pause the simulating at the defined intervals, and during each pause, comparing a measured value for the performance metric to the target value for the performance metric; and ending the simulation when a specified condition based on said comparing is met. In embodiments, when a difference between the measured value for the performance metric and the target value for the performance metric is within a preset tolerance, the pause is ended and the simulation continues.Type: GrantFiled: July 7, 2020Date of Patent: January 24, 2023Assignee: International Business Machines CorporationInventors: Tharunachalam Pindicura, Yan Xia, Karen Yokum, Vivek Britto, Shricharan Srivatsan, Aishwarya Dhandapani
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Patent number: 11321225Abstract: A method, system and computer program product are disclosed for reducing the memory load time for logic simulator. In an embodiment, the method comprises identifying a memory for a program, and selectively loading onto a logic simulator parts of the memory that are pre-determined as parts of the memory that will be accessed by the program when the program is executed on the simulator. In an embodiment, the selectively loading onto a logic simulator parts of the memory includes pre-determining subsets of the memory that will be accessed by the program when the program is executed on the simulator, and loading the pre-determined subsets of the memory on the simulator. In an embodiment, the pre-determining subsets of the memory includes using addresses of the memory that are accessed by the program when the program is executed on a computer system, to create the pre-determined subsets of the memory.Type: GrantFiled: May 22, 2020Date of Patent: May 3, 2022Assignee: International Business Machines CorporationInventors: Tharunachalam Pindicura, Shricharan Srivatsan, Vivek Britto, Yan Xia, Aishwarya Dhandapani
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Publication number: 20220004680Abstract: A method for performing automated detection of transaction latency for a processor design model running an application in a hardware simulation accelerator. The method includes loading the processor design model into the hardware simulation accelerator, loading the application into the processor design model running within the hardware simulation accelerator, simulating the processor design model running the application within the hardware simulation accelerator, and for each individual transaction of the application: establishing a first checkpoint at a start of an execution of the individual transaction by creating a breakpoint and resetting a counter, establishing a second checkpoint at a completion of the transaction by creating another breakpoint and obtaining latency information for the second checkpoint. The latencies of the individual transaction from the start to the completion are measured based on the latency information.Type: ApplicationFiled: July 1, 2020Publication date: January 6, 2022Applicant: International Business Machines CorporationInventors: John A. Schumann, Tharunachalam Pindicura, SHRICHARAN SRIVATSAN, VIVEK BRITTO, Madhumitha Venkataraman
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Publication number: 20210365294Abstract: A method, system and computer program product are disclosed for reducing the memory load time for logic simulator. In an embodiment, the method comprises identifying a memory for a program, and selectively loading onto a logic simulator parts of the memory that are pre-determined as parts of the memory that will be accessed by the program when the program is executed on the simulator. In an embodiment, the selectively loading onto a logic simulator parts of the memory includes pre-determining subsets of the memory that will be accessed by the program when the program is executed on the simulator, and loading the pre-determined subsets of the memory on the simulator. In an embodiment, the pre-determining subsets of the memory includes using addresses of the memory that are accessed by the program when the program is executed on a computer system, to create the pre-determined subsets of the memory.Type: ApplicationFiled: May 22, 2020Publication date: November 25, 2021Inventors: Tharunachalam Pindicura, SHRICHARAN SRIVATSAN, VIVEK BRITTO, YAN XIA, AISHWARYA DHANDAPANI
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Patent number: 11138089Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes generating workload information of a performance base test; determining characteristics of the workload information; determining one or more constraints that can cause behavioral changes to a design of the processor; combining the determined characteristics and the determined one or more constraints to generate one or more example constraints; testing the one or more example constraints in one or more example performance tests; and generating one or more performance benchmarks for the performance base test and the one or more example performance tests.Type: GrantFiled: December 19, 2018Date of Patent: October 5, 2021Assignee: International Business Machines CorporationInventors: Shricharan Srivatsan, Vivek Britto, Aishwarya Dhandapani, Tharunachalam Pindicura, John A. Schumann, Brian W. Thompto
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Patent number: 10754791Abstract: Examples of techniques for software translation prefetch instructions are described herein. An aspect includes, based on encountering a translation prefetch instruction in software that is being executed by a processor, determining whether an address translation corresponding to the translation prefetch instruction is located in a translation lookaside buffer (TLB) of the processor. Another aspect includes, based on determining that the address translation is not located in the TLB, issuing an address translation request corresponding to the translation prefetch instruction. Another aspect includes storing an address translation corresponding to the address translation request in the TLB.Type: GrantFiled: January 2, 2019Date of Patent: August 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vivek Britto, Bryant Cockcroft, John Schumann, Tharunachalam Pindicura, Shricharan Srivatsan, Yan Xia, Aishwarya Dhandapani
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Publication number: 20200210346Abstract: Examples of techniques for software translation prefetch instructions are described herein. An aspect includes, based on encountering a translation prefetch instruction in software that is being executed by a processor, determining whether an address translation corresponding to the translation prefetch instruction is located in a translation lookaside buffer (TLB) of the processor. Another aspect includes, based on determining that the address translation is not located in the TLB, issuing an address translation request corresponding to the translation prefetch instruction. Another aspect includes storing an address translation corresponding to the address translation request in the TLB.Type: ApplicationFiled: January 2, 2019Publication date: July 2, 2020Inventors: VIVEK BRITTO, BRYANT COCKCROFT, John Schumann, Tharunachalam Pindicura, SHRICHARAN SRIVATSAN, YAN XIA, AISHWARYA DHANDAPANI
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Publication number: 20200201739Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes generating workload information of a performance base test; determining characteristics of the workload information; determining one or more constraints that can cause behavioral changes to a design of the processor; combining the determined characteristics and the determined one or more constraints to generate one or more example constraints; testing the one or more example constraints in one or more example performance tests; and generating one or more performance benchmarks for the performance base test and the one or more example performance tests.Type: ApplicationFiled: December 19, 2018Publication date: June 25, 2020Inventors: Shricharan Srivatsan, Vivek Britto, Aishwarya Dhandapani, Tharunachalam Pindicura, John A. Schumann, Brian W. Thompto