Abstract: Methods and deserializer circuits are provided for generating a parallel data signal by converting serial data of a serial data signal to parallel data. In a particular embodiment, the deserializer circuit includes a logic divider configured to generate based on a half rate clock, a quarter rate clock, a mode rate clock, and a selection control signal. The deserializer circuit includes a first set of latches for sampling and aligning the serial data from the serial data signal into the deserializer circuit based on the half rate clock. The deserializer circuit also includes a shift register including a second set of latches configured to latch the output of the first set of latches based on the quarter rate clock generated by the logic divider. In the particular embodiment, the deserializer circuit also includes multiplexer logic configured to output the parallel data signal including latching data from the shift register.

Abstract: Methods and deserializer circuits are provided for generating a parallel data signal by converting serial data of a serial data signal to parallel data. In a particular embodiment, the deserializer circuit includes a logic divider configured to generate based on a half rate clock, a quarter rate clock, a mode rate clock, and a selection control signal. The deserializer circuit includes a first set of latches for sampling and aligning the serial data from the serial data signal into the deserializer circuit based on the half rate clock. The deserializer circuit also includes a shift register including a second set of latches configured to latch the output of the first set of latches based on the quarter rate clock generated by the logic divider. In the particular embodiment, the deserializer circuit also includes multiplexer logic configured to output the parallel data signal including latching data from the shift register.