Abstract: Task distribution is performed in hardware without the use of “division” logic component to divide executions between task execution registers, which advantageously require less silicon when implemented in hardware. Instead, a remainder register is used as a temporary store for the number of task executions yet to distributed to task execution registers. Task execution registers are incremented with a value represented by the data pattern of n MSBs of the number of executions required. Corresponding increment and decrement operations occur until task executions, represented by the data value stored in the remainder register, are effectively distributed to task execution registers.

Abstract: An electrical circuit and method to compare contents of counter circuits. The electrical circuit comprises a first counter circuit and a second counter circuit electrically connected to a flip-flop circuit through a logic circuit and OR gates connected to the flip flop circuit. The first counter circuit is for receiving a first enable signal and generating a first output signal. The second counter circuit is for receiving a second enable signal and generating a second output signal. The first enable signal and the second enable signal are for comparing the first output signal to the second output signal. The flip-flop circuit is for generating a first status signal defining a first relationship between the first output signal and the second output signal. The logic circuit is for generating a second status signal defining a second relationship between the first output signal and the second output signal.

Abstract: A data management layer of a layered protocol system and a method of transmitting data. The data management layer including: a cyclic redundancy check generator connected to a retry buffer through a multiplexer; a sequence number generator connected to the retry buffer through the multiplexer; means for generating a sequence number cyclic redundancy check remainder connected to preset inputs of a cyclic redundancy check remainder latch of the cyclic redundancy check generator; an input data bus connected directly to the cyclic redundancy check generator and connected to the retry buffer through the multiplexer; and an output data bus directly connected to the retry buffer.

Abstract: An electrical circuit and method to compare contents of counter circuits. The electrical circuit comprises a first counter circuit and a second counter circuit electrically connected to a flip-flop circuit through a logic circuit. The first counter circuit is for receiving a first enable signal INC_A and generating a first output signal SIG_A. The second counter circuit is for receiving a second enable signal INC_B and generating a second output signal SIG_B. The first enable signal INC_A and the second enable signal INC_B are for comparing the first output signal SIG_A to the second output signal SIG_B. The flip-flop circuit is for generating a first status signal definining a first relationship between the first output signal SIG_A and the second output signal SIG_B. The logic circuit is for generating a second status signal definining a second relationship between the first output signal SIG_A and the second output signal SIG_B.

Abstract: Task distribution is performed in hardware without the use of “division” logic component to divide executions between task execution registers, which advantageously require less silicon when implemented in hardware. Instead, a remainder register is used as a temporary store for the number of task executions yet to distributed to task execution registers. Task execution registers are incremented with a value represented by the data pattern of n MSBs of the number of executions required. Corresponding increment and decrement operations occur until task executions, represented by the data value stored in the remainder register, are effectively distributed to task execution registers.

Abstract: A memory has a set of address spaces to which token data is written and read. Each address space has a token status bit. A token generator allocates token data to the memory address spaces. Upon a reset occurring, a logic circuit provides logic “0” to the token generator disabling status bit checking control so that all the tokens can be issued sequentially. New token data is allocated to the address spaces sequentially and the respective status bit is updated or maintained as logic “1”. When all address spaces have been allocated, the logic circuit provides the actual state of the status bit to the token generator to control subsequent allocations.