Patents by Inventor Shridhar Atmaram More

Shridhar Atmaram More has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated self-test mechanism for an analog-to-digital converter, a reference voltage source, a low dropout regulator, or a power supply
    Patent number: 11206036
    Abstract: An integrated self-test mechanism for monitoring an analog-to-digital converter (ADC), a reference voltage (Vref) source associated with the ADC, a low-dropout regulator (LDO), or a power supply is provided. In one example, an ADC that is associated with an integrated circuit (IC) can monitor its own Vref, the voltage (VLBO) of an LDO associated with the IC, or the voltage (AVDD) provided to an electrical coupling mechanism in the IC that is coupled to a power supply associated with the IC. The ADC can generate a digital output code based, at least in part, on the Vref and one or more of the VLBO and the AVDD. The digital output code can be used to determine whether one or more of the ADC, the Vref source, the LDO, and the power supply is malfunctioning or nonoperational.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: December 21, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rahul Vijay Kulkarni, Abhijeet Gopal Godbole, Shridhar Atmaram More
  • Sample and hold circuit with indefinite holding time
    Patent number: 11139823
    Abstract: A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: October 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rahul Vijay Kulkarni, Shridhar Atmaram More, Kaustubh Ulhas Gadgil
  • SAMPLE AND HOLD CIRCUIT WITH INDEFINITE HOLDING TIME
    Publication number: 20200252077
    Abstract: A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.
    Type: Application
    Filed: April 23, 2020
    Publication date: August 6, 2020
    Inventors: Rahul Vijay Kulkarni, Shridhar Atmaram More, Kaustubh Ulhas Gadgil
  • INTEGRATED SELF-TEST MECHANISM FOR AN ANALOG-TO-DIGITAL CONVERTER, A REFERENCE VOLTAGE SOURCE, A LOW DROPOUT REGULATOR, OR A POWER SUPPLY
    Publication number: 20200186160
    Abstract: An integrated self-test mechanism for monitoring an analog-to-digital converter (ADC), a reference voltage (Vref) source associated with the ADC, a low-dropout regulator (LDO), or a power supply is provided. In one example, an ADC that is associated with an integrated circuit (IC) can monitor its own Vref, the voltage (VLBO) of an LDO associated with the IC, or the voltage (AVDD) provided to an electrical coupling mechanism in the IC that is coupled to a power supply associated with the IC. The ADC can generate a digital output code based, at least in part, on the Vref and one or more of the VLBO and the AVDD. The digital output code can be used to determine whether one or more of the ADC, the Vref source, the LDO, and the power supply is malfunctioning or nonoperational.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 11, 2020
    Inventors: Rahul Vijay KULKARNI, Abhijeet Gopal GODBOLE, Shridhar Atmaram MORE
  • Sample and hold circuit with indefinite holding time
    Patent number: 10673455
    Abstract: A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: June 2, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rahul Vijay Kulkarni, Shridhar Atmaram More, Kaustubh Ulhas Gadgil
  • SAMPLE AND HOLD CIRCUIT WITH INDEFINITE HOLDING TIME
    Publication number: 20190348993
    Abstract: A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.
    Type: Application
    Filed: May 11, 2018
    Publication date: November 14, 2019
    Inventors: Rahul Vijay Kulkarni, Shridhar Atmaram More, Kaustubh Ulhas Gadgil