Patents by Inventor Shridhar G. Bendi

Shridhar G. Bendi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Testing using analog near end loop back circuit
    Patent number: 9515809
    Abstract: Particular embodiments described herein can offer an electronic device that includes a transmit circuit to form part of a transmit interface, and a receive circuit to form part of a receive interface. The transmit circuit and the receive circuit are to test at least one functional aspect of the electronic device on which the transmit circuit and the receive circuit reside. The transmit circuit and the receive circuit are coupled together by an analog near end loop back connection established through a resistor segment.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: December 6, 2016
    Assignee: Intel Corporation
    Inventors: Sriram Venkatesan, Shridhar G. Bendi
  • TESTING USING ANALOG NEAR END LOOP BACK CIRCUIT
    Publication number: 20140160944
    Abstract: Particular embodiments described herein can offer an electronic device that includes a transmit circuit to form part of a transmit interface, and a receive circuit to form part of a receive interface. The transmit circuit and the receive circuit are to test at least one functional aspect of the electronic device on which the transmit circuit and the receive circuit reside. The transmit circuit and the receive circuit are coupled together by an analog near end loop back connection established through a resistor segment.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 12, 2014
    Inventors: Sriram Venkatesan, Shridhar G. Bendi
  • Method of exhaustively testing an embedded ROM using generated ATPG test patterns
    Patent number: 7568134
    Abstract: A model of the memory device is provided, including a memory array model having a plurality of memory array model locations, and a plurality of decoder models, each associated with a memory array model location. Each memory array model location includes a first data set accessed with the input to that memory array model location in a first state, and a second data set accessed with the input to that memory array model location in a second state. The memory device model is provided to an automatic test pattern generation (ATPG) tool, and a test pattern is generated based on the memory device model.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: July 28, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amit Raj Pandey, Peggy A. Nissen, Shridhar G. Bendi