Abstract: A camera device communicates using a first transceiver configured to transmit and receive, over a first communication protocols, signals for configuring the camera device. Furthermore, the camera device communicates with one or more smart home devices using a second transceiver configured to transmit and receive, over a second communication protocols, signals comprising one or more of alerts, control signals and status information to and from the one or more smart home devices. Furthermore, the camera device communicates using a third transceiver configured to transmit and receive, over a third communication protocols, data corresponding to video captured by the camera device.

Abstract: A camera device communicates using a first transceiver configured to transmit and receive, over a first communication protocols, signals for configuring the camera device. Furthermore, the camera device communicates with one or more smart home devices using a second transceiver configured to transmit and receive, over a second communication protocols, signals comprising one or more of alerts, control signals and status information to and from the one or more smart home devices. Furthermore, the camera device communicates using a third transceiver configured to transmit and receive, over a third communication protocols, data corresponding to video captured by the camera device.

Abstract: An Ethernet switch has at least one ingress/egress port which is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaces each of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit modules which receive GE and FE packets from, and transmit GE and FE packets to, the interfaces.

Abstract: An Ethernet switch has at least one ingress/egress port which is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaces each of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit modules which receive GE and FE packets from, and transmit GE and FE packets to, the interfaces.

Abstract: An Ethernet switch has at least one ingress/egress port 1 which is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaces 3 each of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit modules 5, 7 which receive GE and FE packets from, and transmit GE and FE packets to, the interfaces. If there are 8 such ports in the Ethernet switch, then by switching different numbers of the ports between the two modes, the switch may operate in 9 different modes: as 8 GE ports, 7 GE ports and 8 FE ports, 2 GE ports and 48 FE ports, 1 GE port and 56 FE ports, or simply as 64 FE ports.

Abstract: A method of comparing unmasked bits of an N-bit data key to an N-bit Rule includes dividing the key into C-bit chunks. Each of the chunks is used as an 5 address to extract from memories 12, 13, 14, 21, 22, 23, 24, 31, 32, 33, 34, 41, 42, 43, 44. The memory is preprepared, such that the data stored in the address corresponding to that chunk of the key is 1 or O according to whether a bitwise comparison of that chunk of the data key with the mask is equal to a bitwise comparison of that chunk of the mask and rule. This extracted bit therefore indicates whether the rule is obeyed for that chunk of the data key. The N/C extracted bits for each rule are compared, to determine if the rule is obeyed for the entire data key.

Abstract: A parser system is arranged to receive a data stream (1) having interleaved sections derived from a plurality of different packets, and to extract data from each section as it arrives. The parser system has a scanning section which receives information about each of the sections of data defining which packet it relates to, and employs this information and the properties of the data stream, to identify the locations of layer (2), layer (3) and layer (4) data. This information is passed to parser units (7), (9) which extract data based on this data and also offsets. The offsets for the parser (7) are stored in user-programmable registers (9).

Abstract: A data switch includes ingress ports associated with ingress queues (3) and egress ports associated with egress queues (9). The length of the ingress queues (3) is measured, and the level of broadcast packets arriving at the ingress ports is thereby estimated. Based on this estimate it is determined whether or not the level of broadcast packets is excessive, and in this case broadcast storm control is carried out.

Abstract: A Ethernet switch 1 includes a monitoring unit 9 for policing the amount of traffic on each of a plurality of flows or groups of flows. The monitoring unit has a memory, implemented in hardware as a RAM memory, having a section of each of the flows or groups of flows, and acting as a token bucket for those flows or group of flows.

Abstract: An interface unit for data transfer between a processor bus and an ISDN-based bus is disclosed. The ISDN-based bus is an IOM-2 bus. The interface unit enables access to all available IOM-2 slots, thereby increasing data transfer rate between the processor and IOM-2 buses.

Abstract: An Ethernet switch has at least one ingress/egress port 1 which is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaces 3 each of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit modules 5, 7 which receive GE and FE packets from, and transmit GE and FE packets to, the interfaces. If there are 8 such ports in the Ethernet switch, then by switching different numbers of the ports between the two modes, the switch may operate in 9 different modes: as 8 GE ports, 7 GE ports and 8 FE ports, 2 GE ports and 48 FE ports, 1 GE port and 56 FE ports, or simply as 64 FE ports.

Abstract: An interface unit for data transfer between a processor bus and an ISDN-based bus is disclosed. The ISDN-based bus is an IOM-2 bus. The interface unit enables access to all available IOM-2 slots, thereby increasing data transfer rate between the processor and IOM-2 buses.

Abstract: The present invention relates to a communication circuit arrangement (1) providing a testing functionality. A switch (10) couples internal circuit nodes of a transmission path (2) and a receiver path (3) of an interface communication circuit (1), thereby providing a test signal loop. By feeding a test signal (A) into an input terminal (11) of a transmission path (2) and comparing this original signal (A) with a received signal (B) from output terminal (14) of receiver path (3), functional faults of the circuit are revealed at early development stages. The test method is preferably applicable in communication devices.