Abstract: A method of transmitting data and a data management layer. The method includes: providing a cyclic redundancy check generator connected to a retry buffer through a multiplexer; providing a sequence number generator connected to the retry buffer through the multiplexer; generating a sequence number; generating a sequence number cyclic redundancy check remainder using preset inputs of a cyclic redundancy check remainder latch of the cyclic redundancy check generator; providing an input data bus connected directly to the cyclic redundancy check generator and connected to the retry buffer through the multiplexer; providing an output data bus directly connected to the retry buffer; receiving a data packet on the input data bus; adding the sequence number and the cyclic redundancy check remainder to the data packet to create a modified data packet; storing the modified data packet in the retry buffer; and transmitting the modified data packet using the output data bus.

Abstract: An electrical circuit for comparing contents of counter circuits. The electrical circuit comprises a first counter circuit and a second counter circuit electrically connected to a flip-flop circuit through a logic circuit and OR gates connected to the flip flop circuit. The first counter circuit is for receiving a first enable signal and generating a first output signal. The second counter circuit is for receiving a second enable signal and generating a second output signal. The first enable signal and the second enable signal are for comparing the first output signal to the second output signal. The flip-flop circuit is for generating a first status signal defining a first relationship between the first output signal and the second output signal. The logic circuit is for generating a second status signal defining a second relationship between the first output signal and the second output signal.

Abstract: A method of transmitting data and a data management layer. The method includes: providing a cyclic redundancy check generator connected to a retry buffer through a multiplexer; providing a sequence number generator connected to the retry buffer through the multiplexer; generating a sequence number; generating a sequence number cyclic redundancy check remainder using preset inputs of a cyclic redundancy check remainder latch of the cyclic redundancy check generator; providing an input data bus connected directly to the cyclic redundancy check generator and connected to the retry buffer through the multiplexer; providing an output data bus directly connected to the retry buffer; receiving a data packet on the input data bus; adding the sequence number and the cyclic redundancy check remainder to the data packet to create a modified data packet; storing the modified data packet in the retry buffer; and transmitting the modified data packet using the output data bus.

Abstract: A method for data transfer. The method includes: generating a sequence number and storing the sequence number in a retry buffer; generating a cyclic redundancy check remainder; receiving packet data slices of a data packet; in sequence for each packet data slice received, modifying the cyclic redundancy check remainder using a currently received packet data slice and storing the currently received packet data slice in the retry buffer; and after modifying the cyclic redundancy check remainder using a last received packet data slice, storing the last received packet data slice in the retry buffer, modifying the cyclic redundancy check remainder using the last received packet data slice to create a last cyclic redundancy check remainder and storing the last cyclic redundancy check remainder in the retry buffer, the sequence number, the packet data slices and the last cyclic redundancy check remainder comprising a modified data packet.

Abstract: An electrical circuit for comparing contents of counter circuits. The electrical circuit comprises a first counter circuit and a second counter circuit electrically connected to a flip-flop circuit through a logic circuit and OR gates connected to the flip flop circuit. The first counter circuit is for receiving a first enable signal and generating a first output signal. The second counter circuit is for receiving a second enable signal and generating a second output signal. The first enable signal and the second enable signal are for comparing the first output signal to the second output signal. The flip-flop circuit is for generating a first status signal defining a first relationship between the first output signal and the second output signal. The logic circuit is for generating a second status signal defining a second relationship between the first output signal and the second output signal.

Abstract: An electrical circuit and method to compare contents of counter circuits. The electrical circuit comprises a first counter circuit and a second counter circuit electrically connected to a flip-flop circuit through a logic circuit and OR gates connected to the flip flop circuit. The first counter circuit is for receiving a first enable signal and generating a first output signal. The second counter circuit is for receiving a second enable signal and generating a second output signal. The first enable signal and the second enable signal are for comparing the first output signal to the second output signal. The flip-flop circuit is for generating a first status signal defining a first relationship between the first output signal and the second output signal. The logic circuit is for generating a second status signal defining a second relationship between the first output signal and the second output signal.

Abstract: An electrical circuit and method to compare contents of counter circuits. The electrical circuit comprises a first counter circuit and a second counter circuit electrically connected to a flip-flop circuit through a logic circuit. The first counter circuit is for receiving a first enable signal INC_A and generating a first output signal SIG_A. The second counter circuit is for receiving a second enable signal INC_B and generating a second output signal SIG_B. The first enable signal INC_A and the second enable signal INC_B are for comparing the first output signal SIG_A to the second output signal SIG_B. The flip-flop circuit is for generating a first status signal defining a first relationship between the first output signal SIG_A and the second output signal SIG_B. The logic circuit is for generating a second status signal defining a second relationship between the first output signal SIG_A and the second output signal SIG_B.

Abstract: Scheduling a sequence of tasks quickly using a task list containing a sequence of entries, with each entry indicating whether a task is enabled or disabled for execution. A scheduler block examines the sequence of entries without wasting time in examining entries between those (entries) related to a prior scheduled task and a task to be scheduled next. By not wasting time examining the entries related to the disabled entries, the next task in the sequence of tasks may be scheduled for execution quickly.

Abstract: An additional bit is used in a binary register for detecting register contents in timing and counting applications. A predetermined timing or counting event occurs when the additional bit changes logical states. In one implementation, an additional bit is provided in the most significant bit (MSB) position in a binary register, and is initially set to a logical zero state. When the values in the binary register decrement to zero, the additional (MSB) bit changes logic states to a logical one state, when the zero value in the binary register is decremented in the next clock cycle. A determination is consequently made that the binary register has reached zero.

Abstract: Scheduling a sequence of tasks quickly using a task list containing a sequence of entries, with each entry indicating whether a task is enabled or disabled for execution. A scheduler block examines the sequence of entries without wasting time in examining entries between those (entries) related to a prior scheduled task and a task to be scheduled next. By not wasting time examining the entries related to the disabled entries, the next task in the sequence of tasks may be scheduled for execution quickly.

Abstract: An additional bit is used in a binary register for detecting register contents in timing and counting applications. A predetermined timing or counting event occurs when the additional bit changes logical states. In one implementation, an additional bit is provided in the most significant bit (MSB) position in a binary register, and is initially set to a logical zero state. When the values in the binary register decrement to zero, the additional (MSB) bit changes logic states to a logical one state, when the zero value in the binary register is decremented in the next clock cycle. A determination is consequently made that the binary register has reached zero.