Abstract: Disclosed is a transport stream synchronizing system for synchronizing transport streams output from a plurality of transponders and decoded by a plurality of tuners. The transport stream synchronizing system comprises a tuner selector operable to select one transport stream out of a plurality of transport streams decoded by the plurality of tuners, a transport packet synchronizer operable receive the transport stream selected by the tuner selector, and synchronize the received transport stream; and a transport packet arbiter and router operable to receive a synchronized transport stream from the selected tuner, and route the received synchronized transport stream to a predetermined destination.

Abstract: Disclosed is a method for synchronizing a bitstream, the method comprising comparing an incoming data byte of the bitstream with a predetermined byte pattern; writing a result of the comparison to a current write address in a FIFO; calculating a difference between a current read address in the FIFO and the current write address; asserting a synchronization signal when the difference equals a predetermined value; the result of the comparison is asserted; and an output of the FIFO at the current read address is asserted.

Abstract: A method for testing functionality of a chip checker is disclosed. The checker is arranged for generating a predetermined verification signal when the chip, upon receiving a predetermined input signal, generates a corresponding response signal. The method comprises the steps of developing a model of the chip, the model at least partially emulating at least one response of the chip by generating, upon receiving the predetermined input signal, the corresponding response signal. The method further supplies the developed chip model with the predetermined input signal. The checker is then used to test whether the generated response signal corresponds to the respective predetermined input signal. A failure of the checker to generate the predetermined verification signal indicates checker malfunction.

Abstract: Disclosed is a method for synchronizing a bitstream, the method comprising comparing an incoming data byte of the bitstream with a predetermined byte pattern; writing a result of the comparison to a current write address in a FIFO; calculating a difference between a current read address in the FIFO and the current write address; asserting a synchronization signal when the difference equals a predetermined value; the result of the comparison is asserted; and an output of the FIFO at the current read address is asserted.

Abstract: Disclosed is a transport stream synchronizing system for synchronizing transport streams output from a plurality of transponders and decoded by a plurality of tuners. The transport stream synchronizing system comprises a tuner selector operable to select one transport stream out of a plurality of transport streams decoded by the plurality of tuners, a transport packet synchronizer operable receive the transport stream selected by the tuner selector, and synchronize the received transport stream; and a transport packet arbiter and router operable to receive a synchronized transport stream from the selected tuner, and route the received synchronized transport stream to a predetermined destination.

Abstract: A memory has a set of address spaces to which token data is written and read. Each address space has a token status bit. A token generator allocates token data to the memory address spaces. Upon a reset occurring, a logic circuit provides logic “0” to the token generator disabling status bit checking control so that all the tokens can be issued sequentially. New token data is allocated to the address spaces sequentially and the respective status bit is updated or maintained as logic “1”. When all address spaces have been allocated, the logic circuit provides the actual state of the status bit to the token generator to control subsequent allocations.

Abstract: A method for testing functionality of a chip checker is disclosed. The checker is arranged for generating a predetermined verification signal when the chip, upon receiving a predetermined input signal, generates a corresponding response signal. The method comprises the steps of developing a model of the chip, the model at least partially emulating at least one response of the chip by generating, upon receiving the predetermined input signal, the corresponding response signal. The method further supplies the developed chip model with the predetermined input signal. The checker is then used to test whether the generated response signal corresponds to the respective predetermined input signal. A failure of the checker to generate the predetermined verification signal indicates checker malfunction.

Abstract: A memory has a set of address spaces to which token data is written and read. Each address space has a token status bit. A token generator allocates token data to the memory address spaces. Upon a reset occurring, a logic circuit provides logic “0” to the token generator disabling status bit checking control so that all the tokens can be issued sequentially. New token data is allocated to the address spaces sequentially and the respective status bit is updated or maintained as logic “1”. When all address spaces have been allocated, the logic circuit provides the actual state of the status bit to the token generator to control subsequent allocations.

Abstract: A memory has a set of address spaces to which token data is written and read. Each address space has a token status bit. A token generator allocates token data to the memory address spaces. Upon a reset occurring, a logic circuit provides logic “0” to the token generator disabling status bit checking control so that all the tokens can be issued sequentially. New token data is allocated to the address spaces sequentially and the respective status bit is updated or maintained as logic “1”. When all address spaces have been allocated, the logic circuit provides the actual state of the status bit to the token generator to control subsequent allocations.