Abstract: Various embodiments include methods and devices for implementing scaling memory frequency configuration by a computing device. Embodiments may include comparing at least a memory refresh rate, a memory size, at least one use case bandwidth of transmission between the memory and a system on chip (SoC), and a use case latency of transmission between the memory and the SoC with at least one stored memory refresh rate, at least one stored memory size, at least one stored use case bandwidth of transmission between the memory and the SoC, and at least one stored use case latency of transmission between the memory and the SoC, selecting a memory frequency based on a result of the comparison, and configuring the memory for the memory frequency. Some embodiments may include issuing an alarm indicating changing the use for the memory to be able to achieve a use case parameter.

Abstract: Various embodiments include systems and methods for improving Dynamic Random-Access Memory (DRAM) efficiency and Last Level Cache (LLC) utilization. A computing system may be configured to dynamically adjust DRAM efficiency calculations based on multiple system metrics and conditions (e.g., DDR frequency, density, refresh rates, etc.) for more accurate frequency settings and improved power consumption. The computing system may use a multi-stage approach that includes memory and cache allocation, bandwidth management, and frequency settings. The computing system may fine-tune the DRAM efficiency calculations based on various other factors (e.g., cache miss rates, power consumption, etc.), dynamically modify operational parameters (e.g., DDR frequencies, etc.) in response to specific events or computational tasks, and work in tandem with other system components (e.g., a Last-Level Cache Controller (LLCC), etc.) to improve resource allocation.

Abstract: Various embodiments include methods and devices for implementing scaling memory frequency configuration by a computing device. Embodiments may include comparing at least a memory refresh rate, a memory size, at least one use case bandwidth of transmission between the memory and a system on chip (SoC), and a use case latency of transmission between the memory and the SoC with at least one stored memory refresh rate, at least one stored memory size, at least one stored use case bandwidth of transmission between the memory and the SoC, and at least one stored use case latency of transmission between the memory and the SoC, selecting a memory frequency based on a result of the comparison, and configuring the memory for the memory frequency. Some embodiments may include issuing an alarm indicating changing the use for the memory to be able to achieve a use case parameter.