Abstract: A system for generating a parity check matrix for low-density parity-check (LDPC) codes includes a memory and a processing circuitry that retrieves a base matrix from the memory. The base matrix represents sets of valid and invalid positions for a set of circulant matrices. The processing circuitry determines a value for each valid position based on a heuristic function. The value for each valid position indicates a corresponding circulant matrix of the set of circulant matrices. The processing circuitry replaces each valid position with the corresponding circulant matrix based on the determined value, and each invalid position with a null matrix, to generate the parity check matrix. The parity check matrix thus generated has a high girth and equal distribution of cycles within the parity check matrix.

Abstract: A hard decoder includes an input data handler that receives and rearranges a low-density parity-check (LDPC) codeword, and a variable node updater that iteratively updates the rearranged LDPC codeword to generate an updated LDPC codeword during each decoding iteration of the rearranged LDPC codeword. The hard decoder further includes a syndrome generator that generates a syndrome vector associated with the updated LDPC codeword of each decoding iteration. During each decoding iteration, the rearranged LDPC codeword is updated based on a threshold value and the syndrome vector associated with the updated LDPC codeword of a previous decoding iteration and a validity of the updated LDPC codeword of the previous decoding iteration. The hard decoder further includes an output data handler that extracts a message from the updated LDPC codeword that is valid and outputs the extracted message.

Abstract: A system for generating a parity check matrix for low-density parity-check (LDPC) codes includes a memory and a processing circuitry that retrieves a base matrix from the memory. The base matrix represents sets of valid and invalid positions for a set of circulant matrices. The processing circuitry determines a value for each valid position based on a heuristic function. The value for each valid position indicates a corresponding circulant matrix of the set of circulant matrices. The processing circuitry replaces each valid position with the corresponding circulant matrix based on the determined value, and each invalid position with a null matrix, to generate the parity check matrix. The parity check matrix thus generated has a high girth and equal distribution of cycles within the parity check matrix.

Abstract: A decoder is implemented in a field programmable gate array (FPGA) by performing logic simplification of binary expressions associated with the decoder. To perform the logic simplification, the binary expressions are arranged in a binary matrix. Further, a set of submatrices is formed based on the binary expressions such that rows of each submatrix have common data bits in one or more columns of each submatrix. Based on the common data bits, a set of subexpressions for each submatrix is formed. The set of subexpressions of each submatrix is mapped into look-up table clusters of the FPGA, thereby implementing the decoder in the FPGA.