Abstract: Techniques are provided for zero copy accelerated processing of packets received at a network device according to a session oriented protocol. Each packet comprises a header field and a payload field. Data in the header field of a byte is evaluated to determine whether a sequence number in the header field is equal to an expected sequence number for a given flow of packets. When the sequence number in the header field is equal to the expected sequence number, header data from the header field is stored in a header ring comprising a plurality of socket buffers and payload data is directed to an application buffer pool according to a pointer in a streaming data ring. When the sequence number in the header field is not equal to the expected sequence number, the header data and the payload data are stored in the header ring.

Abstract: Embodiments of a transmit-side scaler and method for processing outgoing information packets using thread-based queues are generally described herein. Other embodiments may be described and claimed. In some embodiments, a process ID stored in a token area may be compared with a process ID of an application that generated an outgoing information packet to obtain a transmit queue. The token area may be updated with a process ID stored in an active threads table when the process ID stored in the token area does not match the process ID of the application.

Abstract: Embodiments of a transmit-side scaler and method for processing outgoing information packets using thread-based queues are generally described herein. Other embodiments may be described and claimed. In some embodiments, a process ID stored in a token area may be compared with a process ID of an application that generated an outgoing information packet to obtain a transmit queue. The token area may be updated with a process ID stored in an active threads table when the process ID stored in the token area does not match the process ID of the application.

Abstract: An input-output memory management unit (IOMMU) and method for tracking memory pages during virtual-machine migration are generally described herein. The IOMMU includes an IOMMU manager to service address translation requests associated with memory pages received from a plurality of I/O devices, and a translation request filter to identify translations previously requested from a translation manager. The IOMMU also includes a device context table to identify whether virtual-machine migration is enabled for memory pages associated with virtual addresses identified in received address translation requests. Based on information in the device context table, the IOMMU manager may send a virtual page identifier to the translation manager identifying a virtual page when virtual-machine migration is enabled to indicate that the virtual page has been accessed. The IOMMU manager refrains from sending the virtual page identifier to the translation manager when the virtual page is listed in the translation request filter.

Abstract: An externally managed security and validation processing device includes a cryptographic processing subsystem configured for performing security or validation services; an application interface configured for communicating security or validation services with an application system; and a secure management interface configured for communicating information, including configuration information for the cryptographic processing system for performing said security or validation services, with a service profile system external to the apparatus without passing said configuration information through the application system. The service profile system can typically also migrate security services provided by one apparatus to another apparatus.

Abstract: A method includes receiving a first interrupt request from a first device instance of a plurality of device instances. The first interrupt request is requesting an interrupt of a processor. The method also includes updating a bit vector based on the first interrupt request. The bit vector comprises a plurality of bits representing an accumulation of interrupt requests. The method further includes generating a gang interrupt comprising the updated bit vector. The method also includes transmitting the gang interrupt to call a first device driver associated with the first interrupt request based on the bits in the bit vector.

Abstract: An input-output memory management unit (IOMMU) and method for tracking memory pages during virtual-machine migration are generally described herein. The IOMMU includes an IOMMU manager to service address translation requests associated with memory pages received from a plurality of I/O devices, and a translation request filter to identify translations previously requested from a translation manager. The IOMMU also includes a device context table to identify whether virtual-machine migration is enabled for memory pages associated with virtual addresses identified in received address translation requests. Based on information in the device context table, the IOMMU manager may send a virtual page identifier to the translation manager identifying a virtual page when virtual-machine migration is enabled to indicate that the virtual page has been accessed. The IOMMU manager refrains from sending the virtual page identifier to the translation manager when the virtual page is listed in the translation request filter.

Abstract: Example embodiments of an IOMMU with translation request management and methods for managing translation requests are generally described herein. Other example embodiments may be described and claimed. In some example embodiments, the IOMMU comprises one or more reorder buffers. Each reorder buffer may be associated with one I/O device and may be used to queue pending translation requests for the associated I/O device. A translation request received from a requesting I/O device may be stored in a reorder buffer associated with the requesting I/O device when the translation request is unable to be serviced or when there are one or more pending translation requests in the reorder buffer.

Abstract: A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system is provided. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender determines trigger values for each of the nodes in the system in order to achieve a particular operation sequence. In addition, a synchronization signal generator is provided to synchronize a timing signal between the sender and receiver nodes. Further, the sender designates one or more receiver nodes and causes them to turn on an interrupt enable register. In this way, the receiver nodes are able to be interrupted by the sender.

Abstract: Embodiments of a transmit-side scaler and method for processing outgoing information packets using thread-based queues are generally described herein. Other embodiments may be described and claimed. In some embodiments, a process ID stored in a token area may be compared with a process ID of an application that generated an outgoing information packet to obtain a transmit queue. The token area may be updated with a process ID stored in an active threads table when the process ID stored in the token area does not match the process ID of the application.

Abstract: Example embodiments of an IOMMU with translation request management and methods for managing translation requests are generally described herein. Other example embodiments may be described and claimed. In some example embodiments, the IOMMU comprises one or more reorder buffers. Each reorder buffer may be associated with one I/O device and may be used to queue pending translation requests for the associated I/O device. A translation request received from a requesting I/O device may be stored in a reorder buffer associated with the requesting I/O device when the translation request is unable to be serviced or when there are one or more pending translation requests in the reorder buffer.

Abstract: A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system is provided. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender determines trigger values for each of the nodes in the system in order to achieve a particular operation sequence. In addition, a synchronization signal generator is provided to synchronize a timing signal between the sender and receiver nodes. Further, the sender designates one or more receiver nodes and causes them to turn on an interrupt enable register. In this way, the receiver nodes are able to be interrupted by the sender.

Abstract: A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender determines trigger values for each of the nodes in the system in order to achieve a particular operation sequence. In addition, a synchronization signal generator is provided to synchronize a timing signal between the sender and receiver nodes. Further, the sender designates one or more receiver nodes and causes them to turn on an interrupt enable register. In this way, the receiver nodes are able to be interrupted by the sender.

Abstract: A system, method, and computer program product is presented for simulating a system of hardware components. Each component is simulated in a hardware definition language such as VERILOG. Each component is represented as a simulated device under test (DUT) that is incorporated into a simulation module. The invention synchronizes the simulation modules by issuing clock credit to each simulation module. Each simulation module can only operate when clock credit is available, and can only operate for some number of clock cycles corresponding to the value of the clock credit. Operation is said to consume the clock credit. After a simulation module has consumed its clock credit, its DUT halts. Once every simulation module has consumed its clock credit and halted, another clock credit can be issued. This allows checkpointing of the operation of each DUT and simulates parallelism of the DUTs using executable images of manageable size.

Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.

Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.

Abstract: A system and method for controlling graphics rendering pipelines. The pipeline is unstalled in response to a display interval complete signal which allows pipeline processing to proceed even at the beginning of a tolerance interval. A stall controller unstalls processing of the graphics data in the graphics rendering pipeline when a display interval complete signal has been generated. A stall token installer inserts stall tokens in between frames of the graphics data. A queue stores frame complete markers in an order matching the order of stall tokens inserted in between frames of graphics data.

Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.

Abstract: A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender determines trigger values for each of the nodes in the system in order to achieve a particular operation sequence. In addition, a synchronization signal generator is provided to synchronize a timing signal between the sender and receiver nodes. Further, the sender designates one or more receiver nodes and causes them to turn on an interrupt enable register. In this way, the receiver nodes are able to be interrupted by the sender.

Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.