Patents by Inventor Shrikant Shah
Shrikant Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12375408Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.Type: GrantFiled: March 29, 2024Date of Patent: July 29, 2025Assignee: Intel CorporationInventors: Stephen Palermo, Bradley Chaddick, Gage Eads, Mrittika Ganguli, Abhishek Khade, Abhirupa Layek, Sarita Maini, Niall McDonnell, Rahul Shah, Shrikant Shah, William Burroughs, David Sonnier
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Patent number: 12289239Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.Type: GrantFiled: January 13, 2023Date of Patent: April 29, 2025Assignee: Intel CorporationInventors: Stephen Palermo, Bradley Chaddick, Gage Eads, Mrittika Ganguli, Abhishek Khade, Abhirupa Layek, Sarita Maini, Niall McDonnell, Rahul Shah, Shrikant Shah, William Burroughs, David Sonnier
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Publication number: 20240267334Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.Type: ApplicationFiled: March 29, 2024Publication date: August 8, 2024Inventors: Stephen Palermo, Bradley Chaddick, Gage Eads, Mrittika Ganguli, Abhishek Khade, Abhirupa Layek, Sarita Maini, Niall McDonnell, Rahul Shah, Shrikant Shah, William Burroughs, David Sonnier
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Publication number: 20230231809Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.Type: ApplicationFiled: January 13, 2023Publication date: July 20, 2023Inventors: Stephen Palermo, Bradley Chaddick, Gage Eads, Mrittika Ganguli, Abhishek Khade, Abhirupa Layek, Sarita Maini, Niall McDonnell, Rahul Shah, Shrikant Shah, William Burroughs, David Sonnier
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Patent number: 11575607Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.Type: GrantFiled: September 11, 2020Date of Patent: February 7, 2023Assignee: INTEL CORPORATIONInventors: Stephen Palermo, Bradley Chaddick, Gage Eads, Mrittika Ganguli, Abhishek Khade, Abhirupa Layek, Sarita Maini, Niall McDonnell, Rahul Shah, Shrikant Shah, William Burroughs, David Sonnier
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Publication number: 20220286399Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.Type: ApplicationFiled: September 11, 2020Publication date: September 8, 2022Inventors: Niall McDonnell, Gage Eads, Mrittika Ganguli, Chetan Hiremath, John Mangan, Stephen Palermo, Bruce Richardson, Edwin Verplanke, Praveen Mosur, Bradley Chaddick, Abhishek Khade, Abhirupa Layek, Sarita Maini, Rahul Shah, Shrikant Shah, William Burroughs, David Sonnier
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Publication number: 20210270691Abstract: The present disclosure relates to moisture-impermeable membranes and discloses a waterproofing membrane for use with leak detection system. The membrane comprises, an intermediate layer fused between upper and lower waterproofing layer. The intermediate layer comprises conductive grid, formed by weaving conductive threads, that define a plurality of zones. Each zone comprises a cross sensor, formed by conductive threads. The conductive grid and the cross sensors are connected to a positive terminal of a power supply and negative terminal is connected to a deck. During leak detection, power supply to a selected cross sensor is disconnected, potential difference is measured between the cross sensor and the grid, and compared with a pre-defined threshold potential difference to identify leakage. The membrane eliminates complex wires and cables structure in comparison with conventional waterproofing and leak detection systems.Type: ApplicationFiled: November 28, 2018Publication date: September 2, 2021Inventor: Shrikant SHAH
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Publication number: 20210075730Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.Type: ApplicationFiled: September 11, 2020Publication date: March 11, 2021Inventors: Stephen Palermo, Bradley Chaddick, Gage Eads, Mrittika Ganguli, Abhishek Khade, Abhirupa Layek, Sarita Maini, Niall McDonnell, Rahul Shah, Shrikant Shah, William Burroughs, David Sonnier
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Patent number: 9496024Abstract: A system on a chip (SOC) includes a processor and a memory system coupled to the processor. The memory system includes a static random access memory (SRAM) bank and a memory controller. The SRAM bank includes a first switch coupled to a SRAM array power supply and a source of a transistor of an SRAM storage cell in an SRAM array. The SRAM bank also includes a second switch coupled to a NWELL power supply and a bulk of the transistor of the SRAM storage cell. The second switch is configured to close prior to the first switch closing during power up of the SRAM array.Type: GrantFiled: December 18, 2015Date of Patent: November 15, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivasa Raghavan Sridhara, Sanjeev Kumar Suman, Premkumar Seetharaman, Keshav Bhaktavatson Chintamani, Atul Ramakant Lele, Raviprakash S. Rao, Parvinder Kumar Rana, Ajith Subramonia, Vipul K. Singhal, Malav Shrikant Shah, Bharath Kumar Poluri
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Patent number: 8527821Abstract: This invention uses multiple codecs to efficiently achieve the right balance between compression and coverage for a given design. This application illustrates a simple example using two codecs including a high compression codec and a low compression codec. The test engineer generates a first set of test patterns using the high compression codec. If this high compression results in unacceptable fault coverage loss, the top-up patterns for additional coverage are generated using the low compression codec. The invention may use multiple codecs serially one after the other. The codecs can be of different types or parameters (such as compression ratio, debug tolerance and combinational codec versus sequential codec).Type: GrantFiled: April 13, 2010Date of Patent: September 3, 2013Assignee: Texas Instruments IncorporatedInventors: Malav Shrikant Shah, Swathi Gangasani, Srivaths Ravi
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Publication number: 20120304031Abstract: This invention uses multiple codecs to efficiently achieve the right balance between compression and coverage for a given design. This application illustrates a simple example using two codecs including a high compression codec and a low compression codec. The test engineer generates a first set of test patterns using the high compression codec. If this high compression results in unacceptable fault coverage loss, the top-up patterns for additional coverage are generated using the low compression codec. The invention may use multiple codecs serially one after the other. The codecs can be of different types or parameters (such as compression ratio, debug tolerance and combinational codec versus sequential codec).Type: ApplicationFiled: April 13, 2010Publication date: November 29, 2012Applicant: Texas Instruments IncorporatedInventors: Malav Shrikant Shah, Swathi Gangasani, Srivaths Ravi
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Publication number: 20070113018Abstract: A discussion of a local memory with at least a command block section and a cache section that facilitates an efficient interrupt processing. The command-block section is allocated on a per interrupt basis and contains pointers to cache-lines. When an interrupt is recognized an interrupt, the proposal uses the pointers in the command-block to prefetch the corresponding cache-lines from the cache section of the local memory, which it loads into its local cache buffer. Thus, when the CPU recognizes an interrupt, the information for the context-switch is already available in cache.Type: ApplicationFiled: November 14, 2005Publication date: May 17, 2007Inventors: Peter Brink, Shrikant Shah, Peter Munguia
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Publication number: 20070005858Abstract: Methods and arrangements to extend message signal interrupt (MSI) transactions with additional data to reduce the latency associated with servicing interrupts included in the transactions are contemplated. Some embodiments may comprise a chipset that transmits the MSI to a processor to service the interrupt. The chipset may identify that a transaction is an extended MSI transaction by determining that the MSI has more than a four bytes. In several embodiments, the chipset may validate the MSI by determining that the MSI comprises at least six bytes and, in further embodiments, by determining that the extended MSI has a valid signature byte. Another embodiment comprises a processor to receive the extended MSI transaction and store the data to service the corresponding interrupt(s) in a low latency buffer. The processor may then service the interrupt(s) based upon the data when the processor becomes available.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Inventors: Shrikant Shah, Peter Brink, Peter Munguia
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Publication number: 20060004946Abstract: A method and apparatus for high performance volatile disk drive (VDD) memory access using an integrated direct memory access (DMA) engine. In one embodiment, the method includes the detection of a data access request to VDD memory implemented within volatile system memory. Once a data access request is detected, a VDD driver may issue a DMA data request to perform the data access request from the VDD. Accordingly, in one embodiment, the job of transferring data to/from a VDD memory implemented within an allocated portion of volatile system memory is offloaded to a DMA engine, such as, for example, an integrated DMA engine within a memory controller hub (MCH). Other embodiments are described and claimed.Type: ApplicationFiled: June 30, 2004Publication date: January 5, 2006Inventors: Shrikant Shah, Chetan Rawal
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Publication number: 20050228917Abstract: An electronic system includes a processor and an interrupt structure. The interrupt structure handles interrupt information such as interrupt requests, interrupt function types, and interrupt data without involving the processor. The processor performs interrupt functions according to the interrupt information at times independent from the times the interrupt requests are received by the interrupt structure.Type: ApplicationFiled: March 30, 2004Publication date: October 13, 2005Inventors: Peter Brink, Shrikant Shah