Patents by Inventor Shrikrishna Nana Mehetre

Shrikrishna Nana Mehetre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Input/output cell wire connector
    Patent number: 10763205
    Abstract: An input/output (I/O) circuit includes at least one I/O cell having a first size, and a high current circuit coupled to the at least one I/O cell. The high current circuit has a second size that is smaller than the first size. A connection bus is coupled to the high current circuit. The connection bus has the second size and is positioned in substantially a same location within the I/O circuit as the high current circuit. A bump or a bond pad is coupled to the connection bus.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: September 1, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Pritesh Pawaskar, Yehuda Smooha, Shrikrishna Nana Mehetre
  • On-die decoupling capacitor area optimization
    Patent number: 10621387
    Abstract: A method includes calculating a maximum value of an on-die decoupling capacitor for an integrated circuit (IC) design based on a switching current defined by a number of simultaneously switching bits for the IC design. The method also includes calculating a total decoupling capacitance value offered by spacer cells in the IC design. The method further includes determining an optimal on-die decoupling capacitance value for the IC design as a function of the maximum value of the on-die decoupling capacitor and the total decoupling capacitance value offered by the spacer cells.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 14, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Nitin Kumar Chhabra, Rohit Halba, Shrikrishna Nana Mehetre
  • Probability-based optimization of system on chip (SOC) power
    Patent number: 10560116
    Abstract: A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: February 11, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Nitin Kumar Chhabra, Rohit Halba, Shashi Kumar Shaw, Shrikrishna Nana Mehetre
  • ON-DIE DECOUPLING CAPACITOR AREA OPTIMIZATION
    Publication number: 20190370425
    Abstract: A method includes calculating a maximum value of an on-die decoupling capacitor for an integrated circuit (IC) design based on a switching current defined by a number of simultaneously switching bits for the IC design. The method also includes calculating a total decoupling capacitance value offered by spacer cells in the IC design. The method further includes determining an optimal on-die decoupling capacitance value for the IC design as a function of the maximum value of the on-die decoupling capacitor and the total decoupling capacitance value offered by the spacer cells.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 5, 2019
    Inventors: Nitin Kumar CHHABRA, Rohit HALBA, Shrikrishna Nana MEHETRE
  • PROBABILITY-BASED OPTIMIZATION OF SOC POWER
    Publication number: 20190199371
    Abstract: A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.
    Type: Application
    Filed: December 26, 2017
    Publication date: June 27, 2019
    Inventors: Nitin Kumar Chhabra, Rohit Halba, Shashi Kumar Shaw, Shrikrishna Nana Mehetre
  • INPUT/OUTPUT CELL WIRE CONNECTOR
    Publication number: 20190019747
    Abstract: An input/output (I/O) circuit includes at least one I/O cell having a first size, and a high current circuit coupled to the at least one I/O cell. The high current circuit has a second size that is smaller than the first size. A connection bus is coupled to the high current circuit. The connection bus has the second size and is positioned in substantially a same location within the I/O circuit as the high current circuit. A bump or a bond pad is coupled to the connection bus.
    Type: Application
    Filed: July 13, 2017
    Publication date: January 17, 2019
    Inventors: Pritesh PAWASKAR, Yehuda Smooha, Shrikrishna Nana Mehetre