Patents by Inventor Shrinath Ramdas

Shrinath Ramdas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12021003
    Abstract: A semiconductor device package includes a semiconductor die having two largest dimensions that define a major plane, a packaging material enclosing the semiconductor die, a plurality of contacts on a first exterior surface of the semiconductor device package that is parallel to the major plane, the first exterior surface defining a bottom of the semiconductor device package, and a pedestal of semiconductor material above the semiconductor die in a thermally-conductive, electrically non-conductive relationship with the semiconductor die. The semiconductor material of the pedestal may be doped to provide electromagnetic shielding of the semiconductor die.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: June 25, 2024
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Han Gao, Ershad Ali, Shrinath Ramdas, Dwayne Richard Shirley, Roberto Coccioli
  • Patent number: 11694971
    Abstract: Embodiments relate to a die package featuring a sputtered metal shield to reduce Electro-Magnetic Interference (EMI). According to a particular embodiment, a die featuring a top surface exposed by surrounding Molded Underfill (MUF) material, is subjected to metal sputtering. The resulting sputtered metal shield is in direct physical and thermal contact with the die, and is in electrical contact with a substrate supporting the die (e.g., to provide shield grounding). Specific embodiments may be particularly suited to reducing the EMI of a package containing an electro-optic die, to between 3-15 dB. The conformal nature and small thickness of the sputtered metal shield desirably conserves space and reduces package footprint. Direct physical contact between the shield and the die surface exposed by the MUF, enhances thermal communication (e.g., reducing junction temperature). According to certain embodiments, the sputtered metal shield comprises a stainless steel liner, copper, and a stainless steel coating.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: July 4, 2023
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Roberto Coccioli, Poorna Chander Ravva, Dwayne Richard Shirley, Jing Li, Shrinath Ramdas, Hassan Kobeissi, Shaohui Yong
  • Publication number: 20230051507
    Abstract: A semiconductor device package includes a semiconductor die having two largest dimensions that define a major plane, a packaging material enclosing the semiconductor die, a plurality of contacts on a first exterior surface of the semiconductor device package that is parallel to the major plane, the first exterior surface defining a bottom of the semiconductor device package, and a pedestal of semiconductor material above the semiconductor die in a thermally-conductive, electrically non-conductive relationship with the semiconductor die. The semiconductor material of the pedestal may be doped to provide electromagnetic shielding of the semiconductor die.
    Type: Application
    Filed: August 12, 2021
    Publication date: February 16, 2023
    Inventors: Han Gao, Ershad Ali, Shrinath Ramdas, Dwayne Richard Shirley, Roberto Coccioli