Patents by Inventor Shrinivas B. Joshi

Shrinivas B. Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10853125
    Abstract: An offload engine may attempt to offload, on behalf of applications, data operations to be performed on a datastream. The offload engine may intercept one or more data operations, such as may be part of a collections API, performed by an application. The data operations and the datastream may be specified and/or provided by the application and, in response, the offload engine may be configured to execute (or attempt to execute) the data operations on the datastream using an analytics accelerating co-processor rather than using a general purpose CPU core. The offload engine may determine whether or not to offload the data operations to the analytics accelerating co-processor. If the offload is unsuccessful or if the offload engine determines that the data operations are not suitable for offloading, the offload engine may then cause the data operations to be performed using general purpose CPU cores on the system.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: December 1, 2020
    Assignee: Oracle International Corporation
    Inventors: Karthik Ganesan, Shrinivas B. Joshi, Yao-Min Chen, Luyang Wang, Ahmed Khawaja
  • Publication number: 20180052708
    Abstract: An offload engine may attempt to offload, on behalf of applications, data operations to be performed on a datastream. The offload engine may intercept one or more data operations, such as may be part of a collections API, performed by an application. The data operations and the datastream may be specified and/or provided by the application and, in response, the offload engine may be configured to execute (or attempt to execute) the data operations on the datastream using an analytics accelerating co-processor rather than using a general purpose CPU core. The offload engine may determine whether or not to offload the data operations to the analytics accelerating co-processor. If the offload is unsuccessful or if the offload engine determines that the data operations are not suitable for offloading, the offload engine may then cause the data operations to be performed using general purpose CPU cores on the system.
    Type: Application
    Filed: October 6, 2016
    Publication date: February 22, 2018
    Inventors: Karthik Ganesan, Shrinivas B. Joshi, Yao-Min Chen, Luyang Wang, Ahmed Khawaja
  • Patent number: 8707282
    Abstract: A technique for prefetching data into a cache memory system includes prefetching data based on meta information indicative of data access patterns. A method includes tagging data of a program with meta information indicative of data access patterns. The method includes prefetching the data from main memory at least partially based on the meta information, by a processor executing the program. In at least one embodiment, the method includes generating an executable at least partially based on the meta information. The executable includes at least one instruction to prefetch the data. In at least one embodiment, the method includes inserting one or more instructions for prefetching the data into an intermediate form of program code while translating program source code into the intermediate form of program code.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: April 22, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shrinivas B. Joshi, Thomas M. Deneau
  • Publication number: 20130165154
    Abstract: A method and system for automatically checking-in patrons by detecting that a user is within a defined boundary and then communicating with the patron to invite them to electronically check-in with a business via a mobile device.
    Type: Application
    Filed: March 13, 2012
    Publication date: June 27, 2013
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventor: Shrinivas B. Joshi
  • Patent number: 8447934
    Abstract: Disclosed herein are a processing unit and a multi-processing unit system that implement a cache-coherency method. Such a multi-processing unit system includes a main memory, a first processing unit, and a second processing unit. The first processing unit and the second processing unit are coupled to the main memory. The first processing unit includes a cache and logic. The cache is configured to store data from the main memory. The logic is configured to maintain an entry in a directory of the cache. The entry indicates whether either of the first processing unit and the second processing unit accesses a data object of a cache line for which the first processing unit is a home node.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: May 21, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Shrinivas B. Joshi
  • Publication number: 20120005432
    Abstract: Disclosed herein are a processing unit and a multi-processing unit system that implement a cache-coherency method. Such a multi-processing unit system includes a main memory, a first processing unit, and a second processing unit. The first processing unit and the second processing unit are coupled to the main memory. The first processing unit includes a cache and logic. The cache is configured to store data from the main memory. The logic is configured to maintain an entry in a directory of the cache. The entry indicates whether either of the first processing unit and the second processing unit accesses a data object of a cache line for which the first processing unit is a home node.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 5, 2012
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Shrinivas B. Joshi
  • Publication number: 20120005592
    Abstract: Methods and apparatus provide for the production of metadata-based user interfaces (UIs) such as graphical user interfaces (GUIs). In one example, keypad descriptor metadata is obtained. The keypad descriptor metadata is data identifying a plurality of available keypad GUIs for a particular data field to control the change from a first keypad GUI to a different keypad GUI. The first keypad GUI is provided for the data field based on the obtained keypad descriptor metadata. A second and different keypad GUI is also provided for the same data field based on the keypad descriptor metadata during the same field population session. In another example, a user interface is provided for a device. The user interface is changed based on a current machine state of an input/output function of the device and based on user interface descriptor metadata associated with an element of the user interface.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 5, 2012
    Inventor: Shrinivas B. Joshi
  • Publication number: 20110145502
    Abstract: A technique for prefetching data into a cache memory system includes prefetching data based on meta information indicative of data access patterns. A method includes tagging data of a program with meta information indicative of data access patterns. The method includes prefetching the data from main memory at least partially based on the meta information, by a processor executing the program. In at least one embodiment, the method includes generating an executable at least partially based on the meta information. The executable includes at least one instruction to prefetch the data. In at least one embodiment, the method includes inserting one or more instructions for prefetching the data into an intermediate form of program code while translating program source code into the intermediate form of program code.
    Type: Application
    Filed: December 14, 2009
    Publication date: June 16, 2011
    Inventors: Shrinivas B. Joshi, Thomas M. Deneau
  • Publication number: 20100138820
    Abstract: An improved system and method are disclosed for processing Java program code. Java source code is annotated with a Module or a ControlFlow annotation. The Java source code is then compiled to produce Java bytecode, which in turn is compiled by a just-in-time compiler to produce native code, which retains the annotations. The native code with annotations is then executed. If a bug is identified during the execution of the native code, an associated Module is selected for debugging, followed by determining associated Java source code segments within the responsible control flow path. Debugging operations are then performed on the associated Java source code segments.
    Type: Application
    Filed: December 1, 2008
    Publication date: June 3, 2010
    Inventor: Shrinivas B. Joshi