Abstract: A method for mapping addresses between one or more master devices and at least one common slave device in a multiprocessor system is provided, the system including a bus interconnect for interfacing between the master devices and the common slave device. The method includes steps of: receiving a first address corresponding to a bus transaction between a given one of the one or more master devices and the common slave device; decoding a unique identifier associated with the given one of the one or more master devices; and generating a second address as a function of the first address and the unique identifier for remapping access to the common slave device by the given one of the one or more master devices.

Abstract: A system and method for optimizing slave transaction ID width based on sparse connection between multiple masters and multiple slaves in a multilayer multilevel interconnect system-on-chip (SOC) architecture are disclosed. In one embodiment, slave transaction ID widths are computed for a first processing subsystem and a second processing subsystem including multiple masters and multiple slaves. Further, a slave transaction ID for each master to any slave in the first processing subsystem and in the second processing subsystem is generated based on the computed slave transaction ID width. Furthermore, sparse connection information between the multiple masters and multiple slaves is determined via a first bus matrix in the first processing subsystem. A first optimized slave transaction ID for each master to any slave in the first processing subsystem is then generated by removing don't care bits in each generated slave transaction ID based on the sparse connection information.

Abstract: A system and method for optimizing slave transaction ID width based on sparse connection between multiple masters and multiple slaves in a multilayer multilevel interconnect system-on-chip (SOC) architecture are disclosed. In one embodiment, slave transaction ID widths are computed for a first processing subsystem and a second processing subsystem including multiple masters and multiple slaves. Further, a slave transaction ID for each master to any slave in the first processing subsystem and in the second processing subsystem is generated based on the computed slave transaction ID width. Furthermore, sparse connection information between the multiple masters and multiple slaves is determined via a first bus matrix in the first processing subsystem. A first optimized slave transaction ID for each master to any slave in the first processing subsystem is then generated by removing don't care bits in each generated slave transaction ID based on the sparse connection information.

Abstract: A system and method for sharing peripheral first-in-first-out (FIFO) resources is disclosed. In one embodiment, a system for utilizing peripheral FIFO resources includes a processor, a first peripheral FIFO controller and a second peripheral FIFO controller coupled to the processor for controlling buffering of first data and second data associated with the processor respectively. Further, the system includes a merge module coupled to the first peripheral FIFO controller and the second peripheral FIFO controller for merging a first FIFO channel associated with the first peripheral FIFO controller and a second FIFO channel associated with the second peripheral FIFO controller based on an operational state of the first FIFO channel and an operational state of the second FIFO channel respectively. Also, the system includes a first FIFO and a second FIFO coupled to the merge module via the first FIFO channel and the second FIFO channel respectively.

Abstract: A system and method for sharing peripheral first-in-first-out (FIFO) resources is disclosed. In one embodiment, a system for utilizing peripheral FIFO resources includes a processor, a first peripheral FIFO controller and a second peripheral FIFO controller coupled to the processor for controlling buffering of first data and second data associated with the processor respectively. Further, the system includes a merge module coupled to the first peripheral FIFO controller and the second peripheral FIFO controller for merging a first FIFO channel associated with the first peripheral FIFO controller and a second FIFO channel associated with the second peripheral FIFO controller based on an operational state of the first FIFO channel and an operational state of the second FIFO channel respectively. Also, the system includes a first FIFO and a second FIFO coupled to the merge module via the first FIFO channel and the second FIFO channel respectively.