Abstract: A power circuit is disclosed. The power circuit includes an input node, a plurality of inductors each connected to an output node, a plurality of phases each configured to provide current to one of the inductors, and a control circuit configured to trigger the phases. The phases are configured to provide current to one of the inductors in response to being triggered by the control circuit, the control circuit is configured to determine a variable time difference between a first phase being triggered and a second phase being triggered, and the time difference is based at least in part on a voltage difference between an input voltage at the input node and an output voltage at the output node.

Abstract: A power circuit is disclosed. The power circuit includes an input node, a plurality of inductors each connected to an output node, a plurality of phases each configured to provide current to one of the inductors, and a control circuit configured to trigger the phases. The phases are configured to provide current to one of the inductors in response to being triggered by the control circuit, the control circuit is configured to determine a variable time difference between a first phase being triggered and a second phase being triggered, and the time difference is based at least in part on a voltage difference between an input voltage at the input node and an output voltage at the output node.

Abstract: A power conversion device includes: a semiconductor substrate; a plurality of controllers formed on the semiconductor substrate; two or more converter phases formed on the semiconductor substrate; two or more programmable components formed on the semiconductor substrate, each of the programmable components connected to a respective one of the two or more converter phases; and an interconnect circuit formed on the semiconductor substrate. The two or more programmable components are programmable to selectively couple the two or more converter phases to the plurality of controllers via the interconnect circuit.

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

Abstract: An integrated circuit includes isolation capacitors which include a silicon dioxide dielectric layer and a polymer dielectric layer over the layer of silicon dioxide. The silicon dioxide dielectric layer and the polymer dielectric layer extend across the integrated circuit. Top plates of the isolation capacitors have bond pads for wire bonds or bump bonds. Bottom plates of the isolation capacitors are connected to components of the integrated circuit. Other bond pads are connected to components in the integrated circuit through vias through the silicon dioxide dielectric layer and the polymer dielectric layer.

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

Abstract: An integrated circuit includes isolation capacitors which include a silicon dioxide dielectric layer and a polymer dielectric layer over the layer of silicon dioxide. The silicon dioxide dielectric layer and the polymer dielectric layer extend across the integrated circuit. Top plates of the isolation capacitors have bond pads for wire bonds or bump bonds. Bottom plates of the isolation capacitors are connected to components of the integrated circuit. Other bond pads are connected to components in the integrated circuit through vias through the silicon dioxide dielectric layer and the polymer dielectric layer.

Abstract: An integrated circuit includes isolation capacitors which include a silicon dioxide dielectric layer and a polymer dielectric layer over the layer of silicon dioxide. The silicon dioxide dielectric layer and the polymer dielectric layer extend across the integrated circuit. Top plates of the isolation capacitors have bond pads for wire bonds or bump bonds. Bottom plates of the isolation capacitors are connected to components of the integrated circuit. Other bond pads are connected to components in the integrated circuit through vias through the silicon dioxide dielectric layer and the polymer dielectric layer.

Abstract: An apparatus for demodulating an Amplitude Shift Keying (ASK) encoded signal is provided. The apparatus comprises a peak detector, a first comparator, a threshold generator, a delay circuit, and a second comparator. The peak detector is configured to detect a peak voltage, and the first comparator is coupled to the peak detector and receives a first threshold voltage. The threshold generator is coupled to the peak detector and is configured to generate a second threshold voltage that is proportional to peak voltage. The delay circuit is coupled to the first comparator, and the second comparator is coupled to the delay circuit and that is coupled to the threshold generator so as to receive the second threshold voltage.

Abstract: An apparatus for demodulating an Amplitude Shift Keying (ASK) encoded signal is provided. The apparatus comprises a peak detector, a first comparator, a threshold generator, a delay circuit, and a second comparator. The peak detector is configured to detect a peak voltage, and the first comparator is coupled to the peak detector and receives a first threshold voltage. The threshold generator is coupled to the peak detector and is configured to generate a second threshold voltage that is proportional to peak voltage. The delay circuit is coupled to the first comparator, and the second comparator is coupled to the delay circuit and that is coupled to the threshold generator so as to receive the second threshold voltage.

Abstract: Methods and apparatus to pre-compensate for in-phase/quadrature (I/Q) distortion in quadrature transmitters are disclosed. A disclosed example method comprises coupling a portion of an analog baseband in-phase signal to an analog baseband quadrature signal through an impedance, and selecting a resistance value for the impedance to pre-distort the analog baseband quadrature signal to compensate for an error introduced by modulation of the analog baseband in-phase signal and the analog baseband quadrature signal.

Abstract: Methods and apparatus to pre-compensate for in-phase/quadrature (I/Q) distortion in quadrature transmitters are disclosed. A disclosed example method comprises coupling a portion of an analog baseband in-phase signal to an analog baseband quadrature signal through an impedance, and selecting a resistance value for the impedance to pre-distort the analog baseband quadrature signal to compensate for an error introduced by modulation of the analog baseband in-phase signal and the analog baseband quadrature signal.

Abstract: A microwave power amplifier is comprised of a plurality of series connected amplifier stages. Each stage is provided with a local negative feedback. The addition of the local voltage feedback distribution networks provide correct voltage distribution and equal current distribution for all transistors, such that the peak-to-peak voltage and current swings of each transistor can be set simultaneously to the values required for efficient amplifier operation. The method applies to both FETs and bipolar transistors. The series connected microwave power amplifier is thus characterized as a stack with local voltage feedback networks which provide an equal distribution of voltage across the transistors in the stack. The amplifier stages can be biased and tuned to collectively operate either as a class A or B amplifier.