Patents by Inventor Shrirang Madhav Yardi

Shrirang Madhav Yardi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146548
    Abstract: A testing system includes one or more processors; and a memory storing instructions that, when executed, cause the one or more processors to: perform, on each array of an SRAM of a System-on-a-Chip (SoC), the SRAM having a plurality of arrays, one or more tests to determine one or more biased cells in the array, generate bias characteristics for each array of the SRAM based on the one or more biased cells of the array, compare bias characteristics of each of the plurality of arrays, select, based on the comparison, an array of the plurality of arrays as a Physically Unclonable Function (PUF) array, and store an identifier of the PUF array into a memory of the SoC.
    Type: Application
    Filed: September 21, 2022
    Publication date: May 2, 2024
    Inventors: Sudhir Satpathy, Renji George Thomas, Shrirang Madhav Yardi
  • Patent number: 11948654
    Abstract: A system on a chip includes a first subsystem comprising a first memory; a second subsystem comprising a second memory; and an always-on subsystem. The always-on subsystem can comprise processing circuitry configured to: in response to a first activation event, signal the first subsystem to initiate repair operations on the first memory, and in response to a second activation event occurring after the first event, signal the second subsystem to initiate repair operations on the second memory.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: April 2, 2024
    Assignee: Meta Platforms Technologies, LLC
    Inventors: Shrirang Madhav Yardi, Dinesh Patil, Neeraj Upasani
  • Publication number: 20240095376
    Abstract: An example method includes identifying, by processing circuitry, a Physically Unclonable Function (PUF) array selected from a static random-access memory (SRAM) device of a System-on-a-Chip (SoC); reading, by the processing circuitry, from a memory, helper data associated with the PUF array and usable for generating a cryptographic key based on the PUF array; determining, by the processing circuitry, whether the helper data associated with the PUF array has been altered after its initial generation by a test system; and in response to determining that the helper data associated with the PUF array has been altered, disabling access to data, software, or functions protected by the cryptographic key generated based on the PUF array.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 21, 2024
    Inventors: Sudhir Satpathy, Renji George Thomas, Shrirang Madhav Yardi
  • Patent number: 11886259
    Abstract: A method by a computing system associated with a set of disjoint devices that includes at least one wearable device includes receiving a request to perform a task. The method further includes determining, based on sensor data associated with the set of disjoint devices, a thermal-constraint differential for each device of the set of disjoint devices. The method further includes determining a plurality of workload assignments needed to be performed to accomplish the task. The method further includes distributing, based on the thermal-constraint differentials of the set of disjoint devices, the plurality of workload assignments to one or more devices of the set of disjoint devices to satisfy one or more power or thermal constraints associated with each device of the set of disjoint devices. The method further includes performing the task by causing the one or more devices to execute the distributed plurality of work assignments.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: January 30, 2024
    Assignee: Meta Platforms Technologies, LLC
    Inventors: Bardia Zandian, Eugene Gorbatov, Pankaj Raghuvanshi, Shrirang Madhav Yardi
  • Publication number: 20230273669
    Abstract: The disclosure describes artificial reality (AR) systems and techniques that enable hierarchical power management of multiple devices within a multi-device AR system. For example, a multi-device AR system includes a device comprising one of a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content. The device comprises a System on a Chip (SoC) that includes a host subsystem and plurality of subsystems. Each subsystem includes a child energy processing unit configured to manage power states for the subsystem. The host subsystem includes a parent energy processing unit configured to direct power management of each of the child energy processing units of the plurality of subsystems.
    Type: Application
    Filed: May 4, 2023
    Publication date: August 31, 2023
    Inventors: Shrirang Madhav Yardi, Alok Kumar Mathur
  • Publication number: 20230252156
    Abstract: Techniques are described for improving security of a boot sequence of a system, such as an artificial reality system. In some examples, a method includes configuring, by a boot sequencing system, attack detection circuitry based on configuration information accessed from a first storage device; after configuring the attack detection circuitry, starting, by the boot sequencing system, a root of trust processor to initiate a boot sequence; enabling access, by the root of trust processor during the boot sequence, to secret information stored in a second storage device.
    Type: Application
    Filed: April 6, 2023
    Publication date: August 10, 2023
    Inventors: Shrirang Madhav Yardi, Neeraj Upasani, Dinesh Patil
  • Patent number: 11675415
    Abstract: The disclosure describes artificial reality (AR) systems and techniques that enable hierarchical power management of multiple devices within a multi-device AR system. For example, a multi-device AR system includes a device comprising one of a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content. The device comprises a System on a Chip (SoC) that includes a host subsystem and plurality of subsystems. Each subsystem includes a child energy processing unit configured to manage power states for the subsystem. The host subsystem includes a parent energy processing unit configured to direct power management of each of the child energy processing units of the plurality of subsystems.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: June 13, 2023
    Assignee: Meta Platforms Technologies, LLC
    Inventors: Shrirang Madhav Yardi, Alok Kumar Mathur
  • Publication number: 20230168729
    Abstract: Systems and methods for peak power control include control circuitry which identifies a condition for a device. The control circuitry can apply the condition for the device to one or more models maintained for a plurality of device processing units of the device to determine one or more performance characteristics for the plurality of processing units. The control circuitry can distribute power credits to the plurality of device processing units of the device according to the determined performance characteristics for the plurality of device processing units, to manage a respective peak power for each respective device processing unit according to a number of the power credits distributed to the respective device processing unit.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 1, 2023
    Inventors: Vlad Fruchter, Nishant Sitapara, Javid Jaffari, Shrirang Madhav Yardi, Bardia Zandian
  • Patent number: 11636210
    Abstract: Techniques are described for improving security of a boot sequence of a system, such as an artificial reality system. In some examples, a method includes configuring, by a boot sequencing system, attack detection circuitry based on configuration information accessed from a first storage device; after configuring the attack detection circuitry, starting, by the boot sequencing system, a root of trust processor to initiate a boot sequence; enabling access, by the root of trust processor during the boot sequence, to secret information stored in a second storage device.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: April 25, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Shrirang Madhav Yardi, Neeraj Upasani, Dinesh Patil
  • Publication number: 20230112115
    Abstract: A method by a computing system associated with a set of disjoint devices that includes at least one wearable device includes receiving a request to perform a task. The method further includes determining, based on sensor data associated with the set of disjoint devices, a thermal-constraint differential for each device of the set of disjoint devices. The method further includes determining a plurality of workload assignments needed to be performed to accomplish the task. The method further includes distributing, based on the thermal-constraint differentials of the set of disjoint devices, the plurality of workload assignments to one or more devices of the set of disjoint devices to satisfy one or more power or thermal constraints associated with each device of the set of disjoint devices. The method further includes performing the task by causing the one or more devices to execute the distributed plurality of work assignments.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 13, 2023
    Inventors: Bardia Zandian, Eugene Gorbatov, Pankaj Raghuvanshi, Shrirang Madhav Yardi
  • Publication number: 20220317760
    Abstract: The disclosure describes artificial reality (AR) systems and techniques that enable hierarchical power management of multiple devices within a multi-device AR system. For example, a multi-device AR system includes a device comprising one of a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content. The device comprises a System on a Chip (SoC) that includes a host subsystem and plurality of subsystems. Each subsystem includes a child energy processing unit configured to manage power states for the subsystem. The host subsystem includes a parent energy processing unit configured to direct power management of each of the child energy processing units of the plurality of subsystems.
    Type: Application
    Filed: January 13, 2022
    Publication date: October 6, 2022
    Inventors: Shrirang Madhav Yardi, Alok Kumar Mathur
  • Patent number: 11256319
    Abstract: The disclosure describes artificial reality (AR) systems and techniques that enable hierarchical power management of multiple devices within a multi-device AR system. For example, a multi-device AR system includes a device comprising one of a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content. The device comprises a System on a Chip (SoC) that includes a host subsystem and plurality of subsystems. Each subsystem includes a child energy processing unit configured to manage power states for the subsystem. The host subsystem includes a parent energy processing unit configured to direct power management of each of the child energy processing units of the plurality of subsystems.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: February 22, 2022
    Assignee: Facebook Technologies, LLC
    Inventors: Shrirang Madhav Yardi, Alok Kumar Mathur
  • Publication number: 20220004639
    Abstract: Techniques are described for improving security of a boot sequence of a system, such as an artificial reality system. In some examples, a method includes configuring, by a boot sequencing system, attack detection circuitry based on configuration information accessed from a first storage device; after configuring the attack detection circuitry, starting, by the boot sequencing system, a root of trust processor to initiate a boot sequence; enabling access, by the root of trust processor during the boot sequence, to secret information stored in a second storage device.
    Type: Application
    Filed: September 1, 2020
    Publication date: January 6, 2022
    Applicant: Facebook Technologies, LLC
    Inventors: Shrirang Madhav Yardi, Neeraj Upasani, Dinesh Patil
  • Publication number: 20220004328
    Abstract: The disclosure describes techniques for hierarchical power management of memory of an artificial reality system to reduce power consumption by the memory. An example device may be a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content for display. The device includes memory divided into multiple memory blocks configurable to operate in a plurality of power modes. The device also includes memory block controllers controlling memory blocks. Each memory block controller controls which power mode in which the corresponding memory block is to operate, independent of any of the other memory blocks. The device includes a memory power controller configured to configure control registers of the memory block controllers to direct the memory block controllers to select one of the plurality of power modes for the memory blocks when the memory blocks are not being accessed.
    Type: Application
    Filed: July 31, 2020
    Publication date: January 6, 2022
    Inventors: Shrirang Madhav Yardi, Gregory Edward Ehmann, Ennio Salemi, George Spatz, Jeffrey Ryden
  • Publication number: 20210157390
    Abstract: The disclosure describes artificial reality (AR) systems and techniques that enable hierarchical power management of multiple devices within a multi-device AR system. For example, a multi-device AR system includes a device comprising one of a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content. The device comprises a System on a Chip (SoC) that includes a host subsystem and plurality of subsystems. Each subsystem includes a child energy processing unit configured to manage power states for the subsystem. The host subsystem includes a parent energy processing unit configured to direct power management of each of the child energy processing units of the plurality of subsystems.
    Type: Application
    Filed: March 25, 2020
    Publication date: May 27, 2021
    Inventors: Shrirang Madhav Yardi, Alok Kumar Mathur