Abstract: Procedures are disclosed to automate constraint and power mode (PM) setup determination for quiescent power supply current (IDDQ) testing of a semiconductor design. Starting with known constraints and PM setup, if available, an estimation is run to obtain minimum, lower bound (LB), expected, upper bound (UB), and maximum IDDQ estimates for individual cells. The estimates are sorted by range (UB-LB), and by elevation (expected-minimum). A constraint is added to control the power of the cell with the highest range. A constraint or a PM entry is added to reduce elevation of the cell with the highest elevation, based on a predetermined property of the cell. With the adjusted constraints and PM setup, the steps are repeated. Iteration continues until (1) the top cells are not custom cells, memories, or macros, or (2) the contributions of the top cells to the design's range and elevation are below predetermined limits.