Patents by Inventor Shruthi Muralidhara HIRIYURU

Shruthi Muralidhara HIRIYURU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12248799
    Abstract: An example method of managing guest time for a virtual machine (VM) supported by a hypervisor of a virtualized host computer includes: configuring, by the hypervisor, a central processing unit (CPU) of the host computer to trap, to the hypervisor, access by guest code in the VM to a physical counter and timer of the CPU; configuring, by the hypervisor, the guest code in the VM to use the physical counter and timer of the CPU rather than a virtual counter and timer of the CPU; trapping, at the hypervisor, an access to the physical counter and timer by the guest code; and executing, by the hypervisor, the access to the physical counter and timer on behalf of the guest code while compensating for an adjustment of a system count of the physical counter and timer to maintain the guest time as scaled with respect to frequency of the physical counter and timer.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: March 11, 2025
    Assignee: VMware LLC
    Inventors: Andrei Warkentin, Ye Li, Alexander Fainkichen, Regis Duchesne, Cyprien Laplace, Shruthi Muralidhara Hiriyuru, Sunil Kumar Kotian
  • Patent number: 12118362
    Abstract: An example method of exception handling in a computer system is described. The computer system includes a physical central processing unit (PCPU) and a system memory, the system memory storing a first stack, a second stack, and a double fault stack associated with the PCPU. The method includes: storing, by an exception handler executing in the computer system, an exception frame on the double fault stack in response to a stack overflow condition of the first stack; switching, by the exception handler, a first stack pointer of the PCPU from pointing to the first stack to pointing to the double fault stack; setting a current stack pointer of the PCPU to the first stack pointer; and executing software on the PCPU with the current stack pointer pointing to the double fault stack.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: October 15, 2024
    Assignee: VMware LLC
    Inventors: Cyprien Laplace, Sunil Kumar Kotian, Andrei Warkentin, Regis Duchesne, Alexander Fainkichen, Shruthi Muralidhara Hiriyuru, Ye Li
  • Publication number: 20240241779
    Abstract: Disclosed are various examples of signaling host kernel crashes to a data processing unit (DPU) management operating system (OS). A host kernel crash handler is installed to a host device. A crash of a host kernel of the host device is detected. This triggers the host kernel crash handler to provide the signal to the DPU device, which executes a DPU side crash handling process based on the signal.
    Type: Application
    Filed: January 17, 2023
    Publication date: July 18, 2024
    Inventors: Jared McNeill, Rohith Jagannathan, Andrei Evgenievich Warkentin, Renaud Benjamin Voltz, Shruthi Muralidhara Hiriyuru, Cyprien Laplace
  • Publication number: 20230195484
    Abstract: An example method of managing guest time for a virtual machine (VM) supported by a hypervisor of a virtualized host computer includes: configuring, by the hypervisor, a central processing unit (CPU) of the host computer to trap, to the hypervisor, access by guest code in the VM to a physical counter and timer of the CPU; configuring, by the hypervisor, the guest code in the VM to use the physical counter and timer of the CPU rather than a virtual counter and timer of the CPU; trapping, at the hypervisor, an access to the physical counter and timer by the guest code; and executing, by the hypervisor, the access to the physical counter and timer on behalf of the guest code while compensating for an adjustment of a system count of the physical counter and timer to maintain the guest time as scaled with respect to frequency of the physical counter and timer.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 22, 2023
    Inventors: Andrei WARKENTIN, Ye LI, Alexander FAINKICHEN, Regis DUCHESNE, Cyprien LAPLACE, Shruthi Muralidhara HIRIYURU, Sunil Kumar KOTIAN
  • Publication number: 20230195487
    Abstract: An example method of virtualizing a host virtual counter and timer in a central processing unit (CPU) of a virtualized host computer includes: creating, by a hypervisor of the host computer in response to power on of a virtual machine (VM), a guest virtual counter, the guest virtual counter comprising a data structure including scaling factors; mapping a shared memory page having the data structure into an address space of memory allocated to the VM; and notifying a guest operating system (OS) of the VM of a location in the address space for the shared memory page having the data structure, the guest OS being paravirtualized to scale the host virtual counter and timer based on the scaling factors of the guest virtual counter.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Inventors: Regis DUCHESNE, Andrei WARKENTIN, Cyprien LAPLACE, Ye LI, Shruthi Muralidhara HIRIYURU, Alexander FAINKICHEN, Sunil Kumar KOTIAN
  • Publication number: 20230195470
    Abstract: An example method of exception handling in a computer system is described. The computer system includes a physical central processing unit (PCPU) and a system memory, the system memory storing a first stack, a second stack, and a double fault stack associated with the PCPU. The method includes: storing, by an exception handler executing in the computer system, an exception frame on the double fault stack in response to a stack overflow condition of the first stack; switching, by the exception handler, a first stack pointer of the PCPU from pointing to the first stack to pointing to the double fault stack; setting a current stack pointer of the PCPU to the first stack pointer; and executing software on the PCPU with the current stack pointer pointing to the double fault stack.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Inventors: Cyprien LAPLACE, Sunil Kumar KOTIAN, Andrei WARKENTIN, Regis DUCHESNE, Alexander FAINKICHEN, Shruthi Muralidhara HIRIYURU, Ye LI
  • Patent number: 11550609
    Abstract: An example method of interfacing with a hypervisor in a computing system is described, which includes a processor having at least three hierarchical privilege levels including a third privilege level more privileged than a second privilege level, the second privilege level more privileged than a first privilege level.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: January 10, 2023
    Assignee: VMware, Inc.
    Inventors: Andrei Warkentin, Cyprien Laplace, Regis Duchesne, Alexander Fainkichen, Shruthi Muralidhara Hiriyuru, Ye Li
  • Patent number: 11113071
    Abstract: A method for booting a computer system includes: loading a first stage bootloader of a plurality of first stage bootloaders from a boot image based on a known configuration of the computer system; executing the first stage bootloader to identify a selected bootbank of a plurality of bootbanks in the boot image based on the known configuration of the computer system; executing, by the first stage bootloader, a second stage bootloader from the boot image with an instruction to boot from the selected bootbank; and executing, by the second stage bootloader, a binary file in the selected bootbank.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: September 7, 2021
    Assignee: VMware, Inc.
    Inventors: Cyprien Laplace, Andrei Warkentin, Shruthi Muralidhara Hiriyuru, Ye Li, Alexander Fainkichen, Regis Duchesne, Sunil Kumar Kotian, Renaud Benjamin Voltz
  • Publication number: 20210224090
    Abstract: An example method of interfacing with a hypervisor in a computing system is described, which includes a processor having at least three hierarchical privilege levels including a third privilege level more privileged than a second privilege level, the second privilege level more privileged than a first privilege level.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 22, 2021
    Inventors: Andrei WARKENTIN, Cyprien LAPLACE, Regis DUCHESNE, Alexander FAINKICHEN, Shruthi Muralidhara HIRIYURU, Ye LI