Abstract: Examples include an apparatus having a plurality of clusters of processor cores; a plurality of memory bandwidth allocators, at least one of the plurality of memory bandwidth allocators per cluster, to apply memory bandwidth settings to one or more processor cores of an associated cluster to dynamically adjust priorities of memory bandwidth allocated for one or more workloads to be processed by the one or more processor cores of the associated cluster; a plurality of memory controllers, at least one of the plurality of memory controllers per cluster of processor cores; a plurality of performance monitors, at least one of the plurality of performance monitors per cluster, to generate performance monitoring statistics by monitoring performance of the one or more workloads by one or more processor cores based at least in part on performance monitoring configuration parameters; and a hardware dynamic resource controller configurable into a plurality of virtual dynamic resource controllers, wherein one virtual dyn

Abstract: In some embodiments, traffic detection circuits are provided to increase an IO fabric frequency when increased IO device traffic is detected.

Abstract: In some embodiments, a proactive Icc_max_p provisioning scheme is provided. when some domains need to achieve peak performance (e.g., frequency), other domains are limited proactively to ensure that total Icc_max_p can stay within the predetermined limits.

Abstract: Disclosed are processor systems having cores with context registers to store priority information for threads to run on the core. They also include circuitry to change the core frequency for the thread based on the priority information.

Abstract: An apparatus includes: at least one core to execute instructions; an interface circuit coupled to the at least one core to perform non-processing operations and interface with one or more platform components; and a power controller coupled to the least one core and the interface circuit. The power controller is to receive at least one efficiency latency parameter to optimize a power-latency tradeoff and control a frequency of the interface circuit based at least in part on an activity level of the at least one core and the at least one efficiency latency parameter. Other embodiments are described and claimed.

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Abstract: Examples include a computing system for receiving memory class of service parameters; setting performance monitoring configuration parameters, based at least in part on the memory class of service parameters, for use by a performance monitor of a memory controller to generate performance monitoring statistics by monitoring performance of one or more workloads by a plurality of processor cores based at least in part on the performance monitoring configuration parameters; receiving the performance monitoring statistics from the performance monitor; and generating, based at least in part on the performance monitoring statistics, a plurality of memory bandwidth settings to be applied by a memory bandwidth allocator to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for the one or more workloads to be processed by the plurality of processor cores.

Abstract: Examples described herein relate to circuitry to utilize a proportional, derivative, integral neural network (PIDNN) controller to adjust one or more parameters allocated to a first group of one or more workloads based on one or more target parameters for a second group of one or more workloads. In some examples, the second group of one or more workloads are a same, lower, or higher priority level than that of the first group of one or more workloads.

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Abstract: Examples include a computing system for receiving memory class of service parameters; setting performance monitoring configuration parameters, based at least in part on the memory class of service parameters, for use by a performance monitor of a memory controller to generate performance monitoring statistics by monitoring performance of one or more workloads by a plurality of processor cores based at least in part on the performance monitoring configuration parameters; receiving the performance monitoring statistics from the performance monitor; and generating, based at least in part on the performance monitoring statistics, a plurality of memory bandwidth settings to be applied by a memory bandwidth allocator to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for the one or more workloads to be processed by the plurality of processor cores.