Patents by Inventor Shruti A. Sethi
Shruti A. Sethi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11494967Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.Type: GrantFiled: February 11, 2021Date of Patent: November 8, 2022Assignee: INTEL CORPORATIONInventors: Balaji Vembu, Murali Ramadoss, David I. Standring, Shruti A. Sethi, Jeffrey S. Frizzell, Alan M. Curtis, Abhishek R. Appu, Joydeep Ray, Altug Koker
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Publication number: 20210312692Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: February 11, 2021Publication date: October 7, 2021Applicant: Intel CorporationInventors: Balaji Vembu, Murali Ramadoss, David I. Standring, Shruti A. Sethi, Jeffrey S. Frizzell, Alan M. Curtis, Abhishek R. Appu, Joydeep Ray, Altug Koker
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Patent number: 10922869Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.Type: GrantFiled: March 27, 2020Date of Patent: February 16, 2021Assignee: INTEL CORPORATIONInventors: Balaji Vembu, Murali Ramadoss, David I. Standring, Shruti A. Sethi, Jeffrey S. Frizzell, Alan M. Curtis, Abhishek R. Appu, Joydeep Ray, Altug Koker
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Publication number: 20200286277Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: March 27, 2020Publication date: September 10, 2020Applicant: Intel CorporationInventors: Balaji Vembu, Murali Ramadoss, David I. Standring, Shruti A. Sethi, Jeffrey S. Frizzell, Alan M. Curtis, Abhishek R. Appu, Joydeep Ray, Altug Koker
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Patent number: 10607392Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.Type: GrantFiled: May 7, 2019Date of Patent: March 31, 2020Assignee: INTEL CORPORATIONInventors: Balaji Vembu, Murali Ramadoss, David I. Standring, Shruti A. Sethi, Jeffrey S. Frizzell, Alan M. Curtis, Abhishek R. Appu, Joydeep Ray, Altug Koker
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Publication number: 20190362535Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: May 7, 2019Publication date: November 28, 2019Applicant: Intel CorporationInventors: Balaji Vembu, Murali Ramadoss, David I. Standring, Shruti A. Sethi, Jeffrey S. Frizzell, Alan M. Curtis, Abhishek R. Appu, Joydeep Ray, Altug Koker
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Patent number: 10332302Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 17, 2017Date of Patent: June 25, 2019Assignee: INTEL CORPORATIONInventors: Balaji Vembu, Murali Ramadoss, David I. Standring, Shruti A. Sethi, Jeffrey S. Frizzell, Alan M. Curtis, Abhishek R. Appu, Joydeep Ray, Altug Koker
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Publication number: 20180300931Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: April 17, 2017Publication date: October 18, 2018Applicant: Intel CorporationInventors: Balaji Vembu, Murali Ramadoss, David I. Standring, Shruti A. Sethi, Jeffrey S. Frizzell, Alan M. Curtis, Abhishek R. Appu, Joydeep Ray, Altug Koker
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Patent number: 9759751Abstract: In one embodiment, a system and method perform a spectral analysis in a power measurement system to determine the total harmonic distortion (“THD”) in a power signal by correlating one or more THD calculation parameters to a sensed period of a voltage input signal. In at least one embodiment, the one or more THD calculation parameters are a number of samples of a voltage, current, or voltage and current components of the power signal that correlate to the sensed period. Because, for example, the period of the power signal can vary or the clock frequency can drift over time, the power measurement system correlates the number of samples with the period and, thus, varies the count of samples over which THD is calculated when the period varies. By correlating the samples with the period, the samples more closely represent a period of the sampled component of the power signal.Type: GrantFiled: January 11, 2013Date of Patent: September 12, 2017Assignee: Cirrus Logic, Inc.Inventor: Shruti Sethi