Patents by Inventor Shruti Rajeev Jaywant

Shruti Rajeev Jaywant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit interconnect structure having metal oxide adhesive layer
    Patent number: 10714386
    Abstract: Integrated circuit interconnect structures having a metal oxide adhesive layer between conductive interconnects and dielectric material, as well as related apparatuses and methods are disclosed herein. For example, in some embodiments, an integrated circuit interconnect structure may include a dielectric layer having 60% or more filler, a conductive layer, and a metal oxide adhesive layer between the dielectric and conductive layers. In some embodiments, the metal oxide adhesive layer may include one or more of aluminum oxide, chromium oxide, and nickel oxide.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: July 14, 2020
    Assignee: Intel Corporation
    Inventor: Shruti Rajeev Jaywant
  • INTEGRATED CIRCUIT INTERCONNECT STRUCTURE HAVING METAL OXIDE ADHESIVE LAYER
    Publication number: 20190164821
    Abstract: Integrated circuit interconnect structures having a metal oxide adhesive layer between conductive interconnects and dielectric material, as well as related apparatuses and methods are disclosed herein. For example, in some embodiments, an integrated circuit interconnect structure may include a dielectric layer having 60% or more filler, a conductive layer, and a metal oxide adhesive layer between the dielectric and conductive layers. In some embodiments, the metal oxide adhesive layer may include one or more of aluminum oxide, chromium oxide, and nickel oxide.
    Type: Application
    Filed: January 10, 2019
    Publication date: May 30, 2019
    Applicant: Intel Corporation
    Inventor: Shruti Rajeev Jaywant
  • Integrated circuit interconnect structure having metal oxide adhesive layer
    Patent number: 10199266
    Abstract: Integrated circuit interconnect structures having a metal oxide adhesive layer between conductive interconnects and dielectric material, as well as related apparatuses and methods are disclosed herein. For example, in some embodiments, an integrated circuit interconnect structure may include a dielectric layer having 60% or more filler, a conductive layer, and a metal oxide adhesive layer between the dielectric and conductive layers. In some embodiments, the metal oxide adhesive layer may include one or more of aluminum oxide, chromium oxide, and nickel oxide.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventor: Shruti Rajeev Jaywant
  • INTEGRATED CIRCUIT INTERCONNECT STRUCTURE HAVING METAL OXIDE ADHESIVE LAYER
    Publication number: 20180182709
    Abstract: Integrated circuit interconnect structures having a metal oxide adhesive layer between conductive interconnects and dielectric material, as well as related apparatuses and methods are disclosed herein. For example, in some embodiments, an integrated circuit interconnect structure may include a dielectric layer having 60% or more filler, a conductive layer, and a metal oxide adhesive layer between the dielectric and conductive layers. In some embodiments, the metal oxide adhesive layer may include one or more of aluminum oxide, chromium oxide, and nickel oxide.
    Type: Application
    Filed: December 26, 2016
    Publication date: June 28, 2018
    Applicant: Intel Corporation
    Inventor: Shruti Rajeev Jaywant