Patents by Inventor Shu-an Lin

Shu-an Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071538
    Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 29, 2024
    Inventors: CHEN-FENG CHANG, YU-CHEN LO, TSUNG-HAN LU, SHU-CHIEH CHANG, CHUN-HAO LIANG, DONG-YU WU, MENG-LIN WU
  • Publication number: 20240055026
    Abstract: A storage drive assembly is provided. The storage drive assembly includes a storage drive sized and shaped for insertion into a slot within a chassis, a latching mechanism coupled to a first end of the storage drive, the latching mechanism including an actuation component actuable to transition the latching mechanism from a locked state in which the latching mechanism restricts displacement of the storage drive relative to the chassis to an unlocked state in which the latching mechanism enables displacement of the storage drive assembly relative to the chassis, and a drive secure cover plate adapted to removably mate with the latching mechanism in the locked state, the mated drive secure cover plate preventing physical access to the actuation component.
    Type: Application
    Filed: August 15, 2022
    Publication date: February 15, 2024
    Inventors: Wu-Shu LIN, Fredrick Anthony CONSTANTINO, Kevin Jay LANGSTON, Chia-Ching HUANG
  • Publication number: 20240056388
    Abstract: Techniques for supporting overlapping network addresses universally are disclosed. A system, process, and/or computer program product for supporting overlapping network addresses universally includes generating at least two virtual routers for a cloud security service, the at least two virtual routers including a first virtual router and a second virtual router, routing cloud security service packets using the first virtual router, and routing enterprise subscriber packets using the second virtual router.
    Type: Application
    Filed: August 10, 2022
    Publication date: February 15, 2024
    Inventors: Jia Chen, Hao Long, Shu Lin
  • Patent number: 11901320
    Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Chia Huang, Tsung-Shu Lin, Cheng-Chieh Hsieh, Wei-Cheng Wu
  • Publication number: 20240048149
    Abstract: A complementary current-steering digital-to-analog converter (DAC) including a p-type DAC as well as an n-type DAC is shown. The p-type DAC has p-type current sources, and the n-type DAC has n-type current sources. The p-type and n-type current sources are coupled to a first input terminal or a second input terminal of a transimpedance amplifier (TIA) according to the digital input of the complementary current-steering DAC. In response to the digital input changing from a first value to a second value that is greater than the first value, one or more n-type current sources connected to the second input terminal of the TIA are switched so that they are connected to the first input terminal of the TIA.
    Type: Application
    Filed: May 29, 2023
    Publication date: February 8, 2024
    Inventors: Chih-Hou TSAI, Chien-Yuan CHENG, Ting-Yu KO, Shu-Lin CHANG
  • Publication number: 20240039478
    Abstract: A circuit with a pseudo class-AB structure is shown. The circuit has an output stage, a first capacitor, and a first impedance component. The output stage has a first PMOS (p-type Metal-Oxide-Semiconductor Field-Effect Transistor) and a first NMOS (n-type MOSFET). The first connection node between the drain terminal of the first PMOS and the drain terminal of the first NMOS is coupled to the first output terminal of the circuit. The first capacitor is coupled between the gate terminal of the first PMOS and the gate terminal of the first NMOS. The first impedance component is coupled in parallel with the first capacitor between the gate terminal of the first PMOS and the gate terminal of the first NMOS.
    Type: Application
    Filed: April 11, 2023
    Publication date: February 1, 2024
    Inventors: Chih-Hou TSAI, Zhao-Hui LIN, Ting-Yu KO, Shu-Lin CHANG, Chien-Yuan CHENG, Shao-Yung LU
  • Publication number: 20240038545
    Abstract: A method of forming a conductive layer of a semiconductor device is described. The method includes forming a hard mask layer on a metal layer overlying a substrate, in which the metal layer includes tungsten. The method further includes patterning the hard mask layer until portions of the metal layer are exposed from the patterned hard mask layer. The method further includes performing a plasma process to the metal layer through the patterned hard mask layer until portions of the substrate are exposed from the etched metal layer, in which a process gas mixture used in the plasma process includes a fluorine based gas, a chlorine based gas, and oxygen.
    Type: Application
    Filed: July 27, 2022
    Publication date: February 1, 2024
    Inventor: Yu Shu LIN
  • Patent number: 11888816
    Abstract: Techniques for providing localization at scale for a cloud-based security service are disclosed. In some embodiments, a system/method/computer program product for providing localization at scale for a cloud-based security service includes receiving a connection request at a network gateway of a cloud-based security service; performing a source Network Address Translation (NAT) from a registered set of public IP addresses associated with a tenant; and providing secure access to a Software as a Service (SaaS) using the cloud-based security service.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: January 30, 2024
    Assignee: Palo Alto Networks, Inc.
    Inventors: Thomas Arthur Warburton, Shu Lin, Devendra Raut, Jialiang Li, Hao Long
  • Patent number: 11880607
    Abstract: A self-repair memory circuit includes a cell array, a controller, a row repair decoder, and a column repair decoder. The cell array includes rows and columns of memory cells. The controller receives an input indicating row repair or column repair, and a repair address shared by the row repair and the column repair of the cell array. The row repair decoder maps the repair address of a defective row to a redundant row of the cell array when the input indicates the row repair. The column repair decoder maps the repair address of a defective column to another column of the cell array when the input indicates the column repair.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: January 23, 2024
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Kim Soon Jway, Shu-Lin Lai, Yi-Ping Kuo
  • Publication number: 20240007431
    Abstract: Described herein are systems, methods, and software to enhance failover operations in a cloud computing environment. In one implementation, a method of operating a first service instance in a cloud computing environment includes obtaining a communication from a computing asset, wherein the communication comprises a first destination address. The method further provides replacing the first destination address with a second destination address in the communication, wherein the second destination address comprises a shared address for failover from a second service instance. After replacing the address, the method determines whether the communication is permitted based on the second destination address, and if permitted, processes the communication in accordance with a service executing on the service instance.
    Type: Application
    Filed: September 12, 2023
    Publication date: January 4, 2024
    Inventors: Shu Lin, Patrick Xu, Eswar Rao Sadaram, Hao Long
  • Patent number: 11855030
    Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and conductive pads. The redistribution circuit structure is located on and electrically connected to the semiconductor die, the redistribution circuit structure includes a first contact pad having a first width and a second contact pad having a second width. The conductive pads are located on and electrically connected to the redistribution circuit structure through connecting to the first contact pad and the second contact pad, the redistribution circuit structure is located between the conductive pads and the semiconductor die. The first width of the first contact pad is less than a width of the conductive pads, and the second width of the second contact pad is substantially equal to or greater than the width of the conductive pads.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Hsuan-Ning Shih
  • Patent number: 11855025
    Abstract: A semiconductor device includes a conductive pad having a first width. The semiconductor device includes a passivation layer over the conductive pad, wherein the passivation layer directly contacts the conductive pad. The semiconductor device includes a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad. The semiconductor device includes an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width. The semiconductor device includes a conductive pillar on the UBM layer.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chita Chuang, Yao-Chun Chuang, Tsung-Shu Lin, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 11855018
    Abstract: A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chen-Hua Yu, Tsung-Shu Lin, Wei-Cheng Wu
  • Publication number: 20230406856
    Abstract: Provided are certain BTK inhibitors, pharmaceutical compositions thereof, and methods of use thereof.
    Type: Application
    Filed: November 16, 2021
    Publication date: December 21, 2023
    Inventors: Haohan TAN, Qihong LIU, Yunling WANG, Lihua JIANG, Shu LIN, Xingdong ZHAO, Weibo WANG
  • Publication number: 20230395719
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.
    Type: Application
    Filed: August 17, 2023
    Publication date: December 7, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
  • Patent number: 11838214
    Abstract: Stateful inspection and classification of packets is disclosed. A first differentiated services header value (DSHV) to associate with a first packet type and a corresponding first quality of service treatment is received from a configuration interface for a first packet type associated with a network traffic flow originating from a first application type. A second DSHV is received from the configuration interface to associate with a second packet type. A first packet having the first packet type is received and the first quality of service treatment is applied to the first packet. A second packet having the second packet type is received and the second quality of service treatment is applied to the second packet.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: December 5, 2023
    Assignee: Palo Alto Networks, Inc.
    Inventors: Philip Kwan, Shu Lin
  • Publication number: 20230386908
    Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate, forming a plurality of metal lines and vias in the plurality of dielectric layers, forming a lower portion of an inner seal ring and a lower portion of an outer seal ring extending into the plurality of dielectric layers, depositing a first dielectric layer over the plurality of metal lines and vias, and etching the first dielectric layer to form an opening penetrating through the first dielectric layer. After the first dielectric layer is etched, a top surface of the lower portion of the inner seal ring is exposed, and an entire topmost surface of the lower portion of the outer seal ring is in contact with a bottom surface of the first dielectric layer. An upper portion of the inner seal ring is then formed to extend into the opening and to join the lower portion of the inner seal ring. A second dielectric layer is deposited to cover the upper portion of the inner seal ring.
    Type: Application
    Filed: August 12, 2022
    Publication date: November 30, 2023
    Inventors: Sheng-Han Tsai, Yuan Sheng Chiu, Chou-Jui Hsu, Tsung-Shu Lin
  • Publication number: 20230378012
    Abstract: In an embodiment, a device includes: a first integrated circuit die; a second integrated circuit die; a gap-fill dielectric between a first sidewall of the first integrated circuit die and a second sidewall of the second integrated circuit die; a protective cap overlapping the gap-fill dielectric, the first sidewall of the first integrated circuit die, and the second sidewall of the second integrated circuit die; and an isolation layer around the protective cap, the isolation layer disposed on the first integrated circuit die, and the second integrated circuit die.
    Type: Application
    Filed: August 26, 2022
    Publication date: November 23, 2023
    Inventors: Der-Chyang Yeh, Chao-Wen Shih, Sung-Feng Yeh, Ta Hao Sung, Min-Chien Hsiao, Chun-Chiang Kuo, Tsung-Shu Lin
  • Publication number: 20230369189
    Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Yu Yeh, Tsung-Shu Lin, Wei-Cheng Wu, Tsung-Yu Chen, Li-Han Hsu, Chien-Fu Tseng
  • Publication number: 20230369162
    Abstract: An apparatus for manufacturing packaged semiconductor devices includes a lower plate having package platforms and clamp guide pins to align an upper plate with the lower plate, and a boat tray having windows configured to receive package devices, and a plurality of upper plates configured to be aligned to respective windows and respective package platforms. Clamping force can be applied by fasteners configured to generate a downward force upon the upper plate. Package devices on the platforms are thus subjected to a clamping force. Load cells measure the clamping force so adjustments can be made.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 16, 2023
    Inventors: Wensen Hung, Tsung-Yu Chen, Tsung-Shu Lin, Chen-Hsiang Lao, Wen-Hsin Wei, Hsien-Pin Hu