Abstract: A periodic metal array structure can be disposed between two antenna modules and include rows of metal unit assemblies that each includes metal units connected to each other in a longitudinal direction. Each metal unit has a first longitudinal strip, two first transverse strips, two second transverse strips, and two second longitudinal strips having shorter longitudinal lengths than that of the first longitudinal strip, and being respectively disposed on the left and right sides of the first longitudinal strip and respectively spaced apart therefrom by intervals at which the second transverse strips are located. The top and bottom ends of the first longitudinal strip are respectively connected with the first transverse strips. At least one first transverse strip can be connected to a first transverse strip of an adjacent metal unit. Each second transverse strip can be connected to the first longitudinal strip and a corresponding second longitudinal strip.

Abstract: A fan-out package includes at least one semiconductor die attached to an interposer structure. a molding compound die frame laterally surrounding the at least one semiconductor die and including a molding compound material, and at least one stress buffer structure located on the interposer structure and including a stress buffer material having a first Young's modulus. The molding compound die frame includes a molding compound material having a second Young's modulus that is greater than the first Young's modulus.

Abstract: The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.

Abstract: A base die is configured to: receive a first data and a first encoded data in a writing phase and perform a first error checking and correction processing, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data; perform a second ECC encoding processing on the first data on which the first error checking and correction processing has been performed, to generate a second encoded data; and choose to transmit a to-be-written data to a memory die based on a selection signal in the writing phase, where the to-be-written data is either an initial data or a second data; and choose to transmit the initial data or third data in a reading phase based on a selection signal.

Abstract: A method for detecting a storage life of a pre-crosslinked material is provided. Tableting is performed on an unaged pre-crosslinked material to obtain crosslinked polyethylene. A crosslinking degree and a mechanical property of the crosslinked polyethylene are measured to obtain reference data. The pre-crosslinked material is heated to obtain a fast-aged pre-crosslinked material. The crosslinking degree and mechanical property of crosslinked polyethylene obtained from the fast-aged pre-crosslinked material are measured to obtain measurement results, which are compared with the reference data. If comparison results all fall within corresponding ranges, the time period of heating is increased by a step to repeat the above steps until the comparison results do not all fall within the corresponding ranges. A result obtained by subtracting the step from the time period of heating is converted into a time period of storage at the room temperature.

Abstract: A base die is configured to receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on the first data and the first encoded data to generate a second encoded data, and transmit a second data to a memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data. The base die is further configured to receive the second data from the memory die in a reading phase, perform a first error checking and correction processing, and transmit a third data in the reading phase.

Abstract: A resonant converter and a voltage conversion method. The resonant converter includes a high-frequency inversion circuit, an inductor-inductor-capacitor (LLC) resonant tank network, and a hybrid rectification circuit. The LLC resonant tank network is separately coupled to the high-frequency inversion circuit and the hybrid rectification circuit. The high-frequency inversion circuit is configured to convert a first direct current voltage into a first alternating current voltage. The LLC resonant tank network is configured to adjust the first alternating current voltage to obtain a second alternating current voltage.

Abstract: A semiconductor device and a method of forming the same are provided. A device includes a substrate, a first isolation structure over the substrate, a first fin and a second fin over the substrate and extending through the first isolation structure, and a hybrid fin extending into the first isolation structure and interposed between the first fin and the second fin. A top surface of the first fin and a top surface of the second fin are above a top surface of the first isolation structure. A top surface of the hybrid fin is above the top surface of the first isolation structure. The hybrid fin includes an upper region, and a lower region under the upper region. The lower region includes a seam. A topmost portion of the seam is below the top surface of the first fin and the top surface of the second fin.

Abstract: A base die is configured to: receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on a first sub-data to generate a second encoded data, and transmit a second data to a memory die in the writing phase; where the second data includes the first sub-data, a second sub-data, the first encoded data, and the second encoded data; the base die is further configured to: receive the second data from the memory die in a reading phase, perform first error checking and correction processing on the first sub-data and the second encoded data, and transmit a third data in the reading phase.

Abstract: A method of explaining prediction results of a machine learning model includes: extracting multiple rules based on a training sample set for training the machine learning model and corresponding known labels; determining one or more matching rules to which a sample to be predicted conforms among the rules; generating an explanation model for the machine learning model, wherein the explanation model provides an explanation of a prediction result generated by the machine learning model with respect to a single sample to be predicted; generating counterfactual rules corresponding to the matching rules respectively; determining training samples conforming to one of the counterfactual rules, and forming a counterfactual candidate set including the determined training samples; and performing multi-objective optimization on the counterfactual candidate set to generate a counterfactual explanation.

Abstract: An interconnection structure, along with methods of forming such, are described. The interconnection structure includes a first portion of a conductive layer, and the conductive layer includes one or more graphene layers. The first portion of the conductive layer includes a first interface portion and a second interface portion opposite the first interface portion, and each of the first and second interface portion includes a metal disposed between adjacent graphene layers. The structure further includes a second portion of the conductive layer disposed adjacent the first portion of the conductive layer, and the second portion of the conductive layer includes a third interface portion and a fourth interface portion opposite the third interface portion. Each of the third and fourth interface portion includes the metal disposed between adjacent graphene layers. The structure further includes a dielectric material disposed between the first and second portions of the conductive layer.

Abstract: Consumption information associated with a user consuming video segments may be obtained. The consumption information may define user engagement during a video segment and/or user response to the video segment. Sets of flight control settings associated with capture of the video segments may be obtained. The flight control settings may define aspects of a flight control subsystem for the unmanned aerial vehicle and/or a sensor control subsystem for the unmanned aerial vehicle. The preferences for the flight control settings of the unmanned aerial vehicle may be determined based upon the first set and the second set of flight control settings. Instructions may be transmitted to the unmanned aerial vehicle. The instructions may include the determined preferences for the flight control settings and being configured to cause the unmanned aerial vehicle to adjust the flight control settings to the determined preferences.

Abstract: A DRAM including following components is provided. A bit line stack structure includes a bit line structure and a hard mask layer. The bit line structure is located on the substrate. The hard mask layer is located on the bit line structure. A dielectric layer is located on the bit line stack structure and has an opening. A contact structure is located on the substrate and includes an active region contact and a capacitor contact. The active region contact is located on the substrate. The top surface of the active region contact is exposed by the opening. The capacitor contact is located in the opening over the active region contact. An isolation layer is located between the hard mask layer and the dielectric layer and between the capacitor contact and the bit line stack structure. An etch stop layer is located between the dielectric layer and the isolation layer.

Abstract: A catalytic cracking process includes a step of contacting a cracking feedstock with a catalytic cracking catalyst in the presence of a radical initiator for reaction under catalytic cracking conditions. The radical initiator contains a dendritic polymer and/or a hyperbranched polymer. The dendritic polymer and the hyperbranched polymer each independently has a degree of branching of about 0.3-1, and each independently has a weight average molecular weight of greater than about 1000. The catalytic cracking process is beneficial to enhancing and accelerating the free radical cracking of petroleum hydrocarbon and promoting the regulation of cracking activity and product distribution; by using the process disclosed herein, the conversion of catalytic cracking can be improved, the yields of ethylene and propylene can be increased, and the yield of coke can be reduced.

Abstract: A flexible light emitting diode (LED) circuit having a first layer, the first layer including a conductive material configured to connect to an LED die, a second layer, the second layer including an electrically insulating material, and a third layer positioned between the first and second layer, the third layer having a first terminal extended electrically connecting tab that extends outward beyond the first layer and the second layer.

Abstract: A method of producing a nanocomposite film includes generating a bilayer film including at least a first layer of at least one nanoparticle and a second layer of at least one material and annealing the bilayer film. A uniform nanocomposite film includes a plurality of nanoparticles dispersed in a polymer matrix, wherein the plurality of nanoparticles form at least 60% by volume of the polymer nanocomposite film.

Abstract: A pixel driving device includes a driving transistor, a pixel driving circuit, an optical sensor circuit, and a reset and reading circuit. Driving transistor controls a light emission device. Pixel driving circuit is connected to the driving transistor and resets according to a first sweep signal. Pixel driving circuit compensates according to a second sweep signal. Pixel driving circuit controls the driving transistor according to a driving signal to drive light emission device. Optical sensor circuit includes a node. Optical sensor circuit resets the node to a voltage level of the driving signal. Light sensing circuit performs sensing to generate a light sensing signal. Reset and reading circuit is connected to the driving transistor, the pixel driving circuit, and the optical sensor circuit. Reset and reading circuit receives a reset and reading signal so as to reset the pixel driving circuit and to read out the light sensing signal.

Abstract: A method and apparatus is disclosed relating to food preparation in commercial kitchens. The disclosed extreme vacuum cooling (EVC) technology and apparatus can work in ultra low pressure conditions with adaptive pressure control to avoid potential liquid splash inside the vacuum chamber caused by un-controlled low pressure conditions. Clean air or inert gas is added into the vacuum chamber so that the chamber pressure can track a setpoint trajectory that may have ramp up periods in order to avoid liquid splash events. The apparatus allows the user to automatically cool various kinds of foods based on a recipe with minimal human interaction and meet food safety regulations.

Abstract: An inspection method and an inspection platform applicable for inspecting a light source used to expose a substrate. The light source is adapted to form an illuminated area on a surface of the substrate. The inspection method includes the following steps: placing at least one inspection component on the surface of the substrate; causing the at least one inspection component and the illuminated area to have a relative movement and a relative speed in a specific direction so as to make the illuminated area move across the at least one inspection component, wherein in the specific direction, the illuminated area is smaller in size than the at least one inspection component; inspecting photon energy of incident light in the illuminated area by the at least one inspection component during the relative movement; and determining optical values of the light source according to the photon energy and the relative speed.

Abstract: A transistor device includes a substrate and a gate structure. The gate structure is disposed on the substrate. The gate structure includes a first metal layer and a refractory metal layer disposed on the first metal layer, wherein the first metal layer is disconnected and the refractory metal layer is disconnected.