Patents by Inventor Shu Chen

Shu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240151948
    Abstract: A photographing optical lens assembly includes, in order from an object side to an image side along an optical axis, a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element has positive refractive power. The second lens element has negative refractive power. The third lens element has an object-side surface being convex in a paraxial region thereof.
    Type: Application
    Filed: January 17, 2024
    Publication date: May 9, 2024
    Inventors: Cheng-Chen LIN, Hsin-Hsuan HUANG, Shu-Yun YANG
  • Patent number: 11978722
    Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate. The chip structure has an inclined sidewall, the inclined sidewall is at an acute angle to a vertical, the vertical is a direction perpendicular to a main surface of the chip structure, and the acute angle is in a range from about 12 degrees to about 45 degrees. The method also includes forming a protective layer to surround the chip structure.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Shen Yeh, Po-Chen Lai, Che-Chia Yang, Li-Ling Liao, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11980040
    Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tai-Yen Peng, Tsung-Hsien Chang, Yu-Shu Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Chung-Te Lin
  • Publication number: 20240146316
    Abstract: A system performs a method of adaptive voltage scaling. The method includes generating a voltage adjustment signal based on a hint from a frequency-locked loop (FLL). The FLL includes an oscillator that generates a clock signal at a clock frequency. The voltage adjustment signal is sent to a power management unit (PMU) to cause the PMU to supply an adjusted operating voltage to the FLL. The method further includes updating a minimum code set according to the adjusted operating voltage and an operating temperature. The clock frequency of the oscillator is generated to match a target frequency according to the adjusted operating voltage and a code determined by the FLL from the minimum code set.
    Type: Application
    Filed: October 19, 2023
    Publication date: May 2, 2024
    Inventors: Yu-Shu Chen, Hsin-Chen Chen, Kuan Hung Lin, Jeng-Yi Lin
  • Patent number: 11969349
    Abstract: An implant for the repair of bone and cartilage that includes a cell conductive zone that contains biopolymeric fibers and an osteoconductive zone that contains biopolymeric fibers and calcium-containing mineral particles. The biopolymeric fibers from one zone overlap with the fibers in the other zone forming a stable physical and mechanical integration of the two zones, thus conferring in vivo stability to the implant.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: April 30, 2024
    Assignee: Collagen Matrix, Inc.
    Inventors: Shu-Tung Li, Hui-Chen Chen, Debbie Yuen
  • Publication number: 20240137764
    Abstract: A user equipment (UE) may attempt to access an edge data network. The UE generates a first credential based on a second credential that was generated for a procedure between the UE and a network. The UE then generates an identifier corresponding to the first credential and generates a message authentication code based on the first credential and a count, wherein the count is associated with an identifier of an edge network client running on the UE. The UE then transmits an application registration request, message to a server associated with an edge data network, the application registration request message including the count, the message authentication code, the identifier corresponding to the first credential, and a public land mobile network identifier (PLMN ID) of the network. The UE then receives an authentication accept message or an authentication reject message from the server associated with the edge data network.
    Type: Application
    Filed: February 19, 2021
    Publication date: April 25, 2024
    Inventors: Shu GUO, Dawei ZHANG, Haijing HU, Hao DUO, Huarui LIANG, Lanpeng CHEN, Mona AGNEL, Ralf ROSSBACH, Sudeep MANITHARA VAMANAN, Xiaoyu QIAO
  • Publication number: 20240132923
    Abstract: Provided is a recombinant microorganism including at least two genes for producing itaconic acid and its derived monomers, and the at least two genes are located on the same expression vector. The at least two genes include one encoding cis-aconitic acid decarboxylase and the other one encoding aconitase, and the genome of the recombinant microorganism includes a gene encoding the molecular chaperone protein GroELS. Also provided is a method for producing itaconic acid by using the microorganism.
    Type: Application
    Filed: March 22, 2023
    Publication date: April 25, 2024
    Inventors: I-Son NG, Jo-Shu CHANG, Chuan-Chieh HSIANG, Yeong-Chang CHEN, Yu-Chiao LIU, Chia-Wei TSAI
  • Publication number: 20240136246
    Abstract: A semiconductor device includes a package structure, a first heat spreader, and a second heat spreader. The first heat spreader is aside the package structure. The second heat spreader is in physical contact with the first heat spreader. The second heat spreader covers a top surface and sidewalls of the package structure. A material of the first heat spreader is different from a material of the second heat spreader.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Yu-Sheng Lin, Po-Chen Lai, Shin-Puu Jeng
  • Patent number: 11967547
    Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hua Wang, Shu-Shen Yeh, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11968530
    Abstract: A network may authenticate a user equipment (UE) to access an edge data network. The network generates a first credential based on a second credential, the second credential generated for a procedure between the UE and a cellular network corresponding to the network component, receives an identifier associated with the first credential from a further network component in response to the UE transmitting an application registration request to a server associated with an edge data network and retrieves the first credential based on the identifier. The network also receives a multi-access edge computing (MEC) authorization parameter, verifies the MEC authorization parameter and transmits an authentication verification response to a second network component.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: April 23, 2024
    Assignee: Apple Inc.
    Inventors: Shu Guo, Dawei Zhang, Fangli Xu, Haijing Hu, Huarui Liang, Mona Agnel, Ralf Rossbach, Sudeep Manithara Vamanan, Xiangying Yang, Yuqin Chen
  • Patent number: 11968908
    Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Han-Ting Lin, Sin-Yi Yang, Yu-Shu Chen, An-Shen Chang, Qiang Fu, Chen-Jung Wang
  • Patent number: 11967582
    Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chin-Hua Wang, Po-Chen Lai, Shu-Shen Yeh, Tsung-Yen Lee, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20240125616
    Abstract: A method of correcting a GPS vehicle trajectory of a vehicle on a roadway for a high-definition map is provided. The method comprises receiving first bitmap data from a first sensor of a first vehicle to create a plurality of first multi-layer bitmaps for the first vehicle using the first bitmap data and receiving second bitmap data from a plurality of second sensors of a plurality of second vehicles to create a plurality of second multi-layer bitmaps. The method further comprises creating first probability density bitmaps and an overall probability density bitmap with a probability density estimation, and matching an image template from each of the first probability density bitmaps with the overall probability density bitmap to define match results. The method further comprises combining the match results to define combined utility values and determining the maximal utility value with the combined utility values.
    Type: Application
    Filed: October 10, 2022
    Publication date: April 18, 2024
    Inventors: Bo Yu, Joon Hwang, Carl P. Darukhanavala, Shu Chen, Vivek Vijaya Kumar, Donald K. Grimm, Fan Bai
  • Publication number: 20240121187
    Abstract: Techniques for deploying IPv6 routing are disclosed. A system, process, and/or computer program product for deploying IPv6 routing includes advertising in Border Gateway Protocol (BGP) a new address-family capability in combination with an existing address-family in a network that supports a plurality of address families, and undoing BGP filters to allow BGP routes to be exchanged at a time that a network administrator enables the new address-family capability in the network.
    Type: Application
    Filed: October 6, 2022
    Publication date: April 11, 2024
    Inventors: Jia Chen, Shu Lin, Jining Tian, Enke Chen
  • Publication number: 20240119471
    Abstract: According to the embodiments of the present disclosure, a method for conversion evaluation comprises: extracting a resource feature from resource-related data of a target resource; extracting an audience feature of the target audience group from audience-related data of a target audience group of the target resource, the target audience group being to be distributed with a recommended content item related to the target resource; and determining, based on the resource feature and the audience feature, a target predicted conversion rate for the target resource through a predetermined association between resource features, audience features and predicted conversion rates, the target predicted conversion rate indicating a predicted probability of the target audience group performing a conversion for the target resource. According to the scheme, the accuracy of the conversion rate evaluation may be improved, thereby improving distribution effect of the recommended content item for a resource.
    Type: Application
    Filed: September 22, 2023
    Publication date: April 11, 2024
    Inventors: Xiaowang Kong, Shu Chen, Zhibin Wu, Zhe Wang, Haiqian HE
  • Patent number: 11956421
    Abstract: Method and apparatus of video coding are disclosed. According to one method, in the decoder side, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block when the neighboring block satisfies one or more conditions. An MPM (Most Probable Mode) list is derived based on information comprising at least one of neighboring Intra modes. A current Intra mode is derived utilizing the MPM list. The current luma block is decoded according to the current Intra mode According to another method, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block if the neighboring block is coded in BDPCM (Block-based Delta Pulse Code Modulation) mode, where the predefined Intra mode is set to horizontal mode or vertical mode depending on prediction direction used by the BDPCM mode.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: April 9, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang, Shih-Ta Hsiang
  • Patent number: 11956469
    Abstract: Video processing methods and apparatuses implemented in a video encoding or decoding system with conditional secondary transform signaling. The video encoding system determines and applies a transform operation to residuals of a transform block to generate final transform coefficients, and adaptively signals a secondary transform index according to a position of a last significant coefficient in the transform block. A value of the secondary transform index is determined according to the transform operation.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: April 9, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen
  • Publication number: 20240113166
    Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.
    Type: Application
    Filed: February 15, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ging Lin, Chun-Liang Lai, Yun-Chen Wu, Ya-Yi Tsai, Shu-Yuan Ku, Shun-Hui Yang
  • Publication number: 20240114810
    Abstract: A semiconductor structure includes: an etch-stop dielectric layer overlying a substrate and including a first opening therethrough; a silicon oxide plate overlying the etch-stop dielectric layer and including a second opening therethrough; a first conductive structure including a first electrode and extending through the second opening and the first opening; a memory film contacting a top surface of the first conductive structure and including a material that provides at least two resistive states having different electrical resistivity; and a second conductive structure including a second electrode and contacting a top surface of the memory film.
    Type: Application
    Filed: April 20, 2023
    Publication date: April 4, 2024
    Inventors: Fu-Ting Sung, Jhih-Bin Chen, Hung-Shu Huang, Hong Ming Liu, Hsia-Wei Chen, Yu-Wen Liao, Wen-Ting Chu
  • Patent number: D1024640
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: April 30, 2024
    Assignees: King Slide Works Co., Ltd., King Slide Technology Co., Ltd.
    Inventors: Fang-Cheng Su, Ci-Bin Huang, Ching-Fu Chiu, Shu-Chen Lin