Patents by Inventor Shu Cheng

Shu Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250259889
    Abstract: A method includes forming a first conductive feature in a first dielectric layer. A second dielectric layer is formed over the first conductive feature and the first dielectric layer. An opening is formed in the second dielectric layer. The opening exposes a top surface of the first conductive feature. The top surface of the first conductive feature includes a first metallic material and a second metallic material different from the first metallic material. A native oxide layer is removed from the top surface of the first conductive feature. A surfactant soaking process is performed on the top surface of the first conductive feature. The surfactant soaking process forms a surfactant layer over the top surface of the first conductive feature. A first barrier layer is deposited on a sidewall of the opening. The surfactant layer remains exposed at the end of depositing the first barrier layer.
    Type: Application
    Filed: April 28, 2025
    Publication date: August 14, 2025
    Inventors: Yao-Min Liu, Chia-Pang Kuo, Shu-Cheng Chin, Chih-Chien Chi, Cheng-Hui Weng, Hung-Wen Su, Ming-Hsing Tsai
  • Patent number: 12366682
    Abstract: A display device includes a display module and an anti-glare film on the display module. The anti-glare film includes a first anti-glare layer and a second anti-glare layer. The first anti-glare layer has a plurality of microstructures at an upper surface of the first anti-glare layer. A root-mean-square slope of the microstructures is more than 0 and is 0.2 or less. The second anti-glare layer is between the first anti-glare layer and the display module, and an inner haze of the second anti-glare layer is from 20% to 90%.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: July 22, 2025
    Assignee: AUO CORPORATION
    Inventors: Shu-Cheng Kung, Ya-Chen Kao, Ken-Yu Liu
  • Patent number: 12354958
    Abstract: Various back end of line (BEOL) layer formation techniques described herein enable reduced contact resistance, reduced surface roughness, and/or increased semiconductor device performance for BEOL layers such as interconnects and/or metallization layers.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: July 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Cheng Chin, Chih-Chien Chi, Hsin-Ying Peng, Jau-Jiun Huang, Ya-Lien Lee, Kuan-Chia Chen, Chia-Pang Kuo, Yao-Min Liu
  • Publication number: 20250218409
    Abstract: A display device, comprising a display panel, a signal processor and an image processor. The display panel comprises a driving circuit and multiple pixel circuits. The driving circuit is configured to provide multiple driving voltages to the pixel circuits. The signal processor is coupled to the display panel to receive a first image signal. The image processor is coupled to the signal processor, and is configured to receive the first image signal from the signal processor. The signal processor is further configured to output multiple first voltage data according to the first image signal. The signal processor is configured to receive the first voltage data from the image processor, and is configured to convert the first voltage data into a first driving signal. The first driving signal is configured to cause the driving circuit to provide the driving voltages to the pixel circuits.
    Type: Application
    Filed: January 2, 2025
    Publication date: July 3, 2025
    Inventors: Shu-Cheng LIU, Hsiao-Lung CHENG, Pei-Lin TIEN, Chi-Mao HUNG
  • Publication number: 20250209961
    Abstract: A pixel circuit driving method comprising: receiving an image signal, wherein the image signal comprises multiple pixel values; using a first lookup table to obtain multiple first voltage data corresponding to the multiple pixel values in a first original frame; using a second lookup table to generate a multiple first voltage combinations according to the multiple first voltage data, wherein each of the multiple first voltage combinations comprises multiple update voltages, and the multiple first voltage combinations correspond to a multiple first update frames; generating the multiple update voltages to multiple driving multiplexing circuits according to each of the multiple first voltage combinations by multiple power generating circuits; and using the multiple update voltages as multiple driving voltages to provided to multiple pixel circuits by the multiple power generating circuits.
    Type: Application
    Filed: December 19, 2024
    Publication date: June 26, 2025
    Inventors: Shu-Cheng LIU, Hsiao-Lung CHENG, Pei-Lin TIEN, Chi-Mao HUNG
  • Patent number: 12334397
    Abstract: A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Cheng Chin, Chih-Yi Chang, Wei Hsiang Chan, Chih-Chien Chi, Chi-Feng Lin, Hung-Wen Su
  • Publication number: 20250192052
    Abstract: A graphene liner deposited between at least one liner material (e.g., barrier layer, ruthenium liner, and/or cobalt liner) and a copper conductive structure reduces surface scattering at an interface between the at least one liner material and the copper conductive structure. Additionally, or alternatively, the carbon-based liner reduces contact resistance at an interface between the at least one liner material and the copper conductive structure. A carbon-based cap may additionally or alternatively be deposited on a metal cap, over the copper conductive structure, to reduce surface scattering at an interface between the metal cap and an additional copper conductive structure deposited over the metal cap.
    Type: Application
    Filed: February 14, 2025
    Publication date: June 12, 2025
    Inventors: Shu-Cheng CHIN, Chih-Yi CHANG, Chih-Chien CHI, Ming-Hsing TSAI
  • Publication number: 20250183161
    Abstract: A method of making semiconductor device includes forming an insulating layer. The method further includes patterning the insulating layer to define a via opening and a conductive line opening. The method further includes forming a via in the via opening. The method further includes forming a conductive line in the conductive line opening. Forming the conductive line includes forming a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and forming a conductive fill, wherein the first liner layer surrounds the conductive fill.
    Type: Application
    Filed: February 13, 2025
    Publication date: June 5, 2025
    Inventors: Shu-Cheng CHIN, Yao-Min LIU, Hung-Wen SU, Chih-Chien CHI, Chi-Feng LIN
  • Patent number: 12322649
    Abstract: A method includes forming a first conductive feature in a first dielectric layer. A second dielectric layer is formed over the first conductive feature and the first dielectric layer. An opening is formed in the second dielectric layer. The opening exposes a top surface of the first conductive feature. The top surface of the first conductive feature includes a first metallic material and a second metallic material different from the first metallic material. A native oxide layer is removed from the top surface of the first conductive feature. A surfactant soaking process is performed on the top surface of the first conductive feature. The surfactant soaking process forms a surfactant layer over the top surface of the first conductive feature. A first barrier layer is deposited on a sidewall of the opening. The surfactant layer remains exposed at the end of depositing the first barrier layer.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao-Min Liu, Chia-Pang Kuo, Shu-Cheng Chin, Chih-Chien Chi, Cheng-Hui Weng, Hung-Wen Su, Ming-Hsing Tsai
  • Patent number: 12315764
    Abstract: A barrier layer is selectively formed on a bottom surface of a recess (e.g., in which a back end of line (BEOL) conductive structure will be formed) using a combination of flash physical vapor deposition with atomic layer deposition. Additionally, a ruthenium liner is selectively deposited on sidewalls of the BEOL conductive structure using a blocking material. Accordingly, the barrier layer prevents diffusion of metal ions from the BEOL conductive structure and is thinner at the bottom surface as compared to the sidewalls in order to reduce contact resistance. Additionally, the ruthenium liner improves copper flow into the BEOL conductive structure and is thinner at the bottom surface in order to further reduce contact resistance.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: May 27, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Cheng Chin, Chih-Chien Chi, Chi-Feng Lin
  • Publication number: 20250166549
    Abstract: A display device with adjustable grayscale values and a display method thereof are provided. The display device includes a display panel, a communication interface, and a controller. The communication interface is used to receive display data of a display screen. The controller is electrically connected to the display panel and the communication interface, and is used to drive the display panel to display a display screen according to the display data. In response to the controller performing the flashbang assist function, the controller analyzes the display data to detect multiple grayscale values of multiple pixels in the display screen. In response to the controller detecting that the grayscale values of the pixels in the display screen are all higher than or equal to the first threshold, the controller adjusts the display data to reduce at least part of the grayscale values.
    Type: Application
    Filed: September 24, 2024
    Publication date: May 22, 2025
    Applicant: GIGA-BYTE TECHNOLOGY CO.,LTD.
    Inventors: Shu-Cheng Wu, Kuei-Shan Chang, Shih-Chieh Chou
  • Publication number: 20250161809
    Abstract: Disclosed is a display device and a display method for dynamically adjusting a ballistic path. The display device includes a display panel, a communication interface, and a controller. The communication interface is electrically connected to an input device and a host device and is used to receive display data of a display image from the host device and to receive direction data and distance data from the input device. The controller is electrically connected to the display panel and the communication interface and is used to drive the display panel to display the display image according to the display data. The controller further displays a ballistic path image in the display image through the display panel, and the controller dynamically adjusts the ballistic path image according to the direction data and the distance data.
    Type: Application
    Filed: September 24, 2024
    Publication date: May 22, 2025
    Applicant: GIGA-BYTE TECHNOLOGY CO.,LTD.
    Inventors: Shu-Cheng Wu, Kuei-Shan Chang, Shih-Chieh Chou
  • Publication number: 20250138225
    Abstract: A display panel includes a display module and an anti-glare layer. The display module has a pixel density PPI, and the display module includes an upper substrate. The anti-glare layer is over the display module. A top surface of the anti-glare layer has a plurality of microstructures, and the microstructures have a root mean square slope R?q. A thickness L from a bottom of the upper substrate of the display module to a top of the anti-glare layer complies with a following relational expression: L > 0.001 * PPI R ? ? ? q .
    Type: Application
    Filed: December 22, 2023
    Publication date: May 1, 2025
    Inventors: Shu-Cheng KUNG, Jia-Hong Wang, Ya-Ling Hsu, Chen-Hsien Liao
  • Publication number: 20250139973
    Abstract: An object detection device and a confidence threshold method adjustment method are provided. The object detection device includes an optical camera, multiple sensors, and a processor. The optical camera and sensors are used to respectively capture a real-time video and environmental value of a detection area. The processor performs an object recognition model and at least one second recognition model. The object recognition model determines whether an object exists in the detection area based on the real-time video to generate a first recognition result and a corresponding first confidence value. The at least one second recognition model generates a second result based on the environmental value respectively. The processor dynamically adjusts a confidence threshold value based on a value of the second result and a correlation degree between the object and the second result.
    Type: Application
    Filed: September 29, 2024
    Publication date: May 1, 2025
    Applicant: VIA Technologies, Inc.
    Inventors: Chung-Ching Huang, Shu-Cheng Chi, Kuo-Han Chang
  • Publication number: 20250132162
    Abstract: A semiconductor substrate processing method includes: providing a substrate to be processed, where the substrate to be processed has a side to be processed and a bonding side which are opposite to each other; providing a hole supply substrate; and bonding the hole supply substrate to the bonding side of the substrate to be processed by a wafer bonding process so as to obtain a substrate pair, and performing a material process. By the semiconductor substrate processing method, the purpose of rapid electrochemical etching can be achieved.
    Type: Application
    Filed: April 12, 2024
    Publication date: April 24, 2025
    Inventors: Tien-Hsi LEE, CHUN-HUANG WU, YU-SHENG CHIOU, SHU-CHENG LI, JING-SYONG HUANG, GUAN-YU LIN, WEI-CHI HUANG
  • Publication number: 20250125309
    Abstract: Vertically stacked semiconductor devices and methods of fabrication thereof that include a first device structure bonded to a second device structure via bonding layers having compressible metal bonding structures. The compressible metal bonding structures may be fabricated using an electroless deposition (ED) process, and may be less dense with a greater degree of compressibility than equivalent materials deposited by related processes. Accordingly, mating pairs of metal bonding structures may have a degree of compliance that enables effective metal-to-metal contact during a subsequent bonding process. Recrystallization of the metal material during an annealing process may produce shrinkage of the metal material and the formation of void areas between the metal bonds and the surrounding dielectric layers, thereby reducing stress on the surrounding dielectric-to-dielectric interface.
    Type: Application
    Filed: October 11, 2023
    Publication date: April 17, 2025
    Inventors: Kai-Hsiang Yang, Chin-Fu Kao, Amram Eitan, Shu-Cheng Lin
  • Patent number: 12277423
    Abstract: The present invention discloses a processor control method including: controlling a processor to execute a first operating system in a first state; when the processor executing the first operating system satisfies a predetermined condition, controlling the processor to switch from the first state to a second state; and controlling the processor to execute a second operating system in the second state, wherein an authority of the first state is higher than an authority of the second state.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: April 15, 2025
    Assignee: SIGMASTAR TECHNOLOGY LTD.
    Inventors: Cheng-Chi Huang, Shu-Cheng Chou, Yu-Hsiang Lin
  • Patent number: 12255144
    Abstract: A graphene liner deposited between at least one liner material (e.g., barrier layer, ruthenium liner, and/or cobalt liner) and a copper conductive structure reduces surface scattering at an interface between the at least one liner material and the copper conductive structure. Additionally, or alternatively, the carbon-based liner reduces contact resistance at an interface between the at least one liner material and the copper conductive structure. A carbon-based cap may additionally or alternatively be deposited on a metal cap, over the copper conductive structure, to reduce surface scattering at an interface between the metal cap and an additional copper conductive structure deposited over the metal cap.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Cheng Chin, Chih-Yi Chang, Chih-Chien Chi, Ming-Hsing Tsai
  • Publication number: 20250076340
    Abstract: Some embodiments relate to a method of an integrated circuit structure having a conductive structure for circuit probe testing. The method includes providing an integrated circuit structure including a substrate, a dielectric structure disposed over the substrate, and a plurality of electrodes disposed over an upper surface of the dielectric structure. The method also includes forming a first dielectric layer over the dielectric structure and the plurality of electrodes, etching the first dielectric layer over each of the plurality of electrodes, forming a conductive layer over the first dielectric layer and the plurality of electrodes, and removing at least a portion of the conductive layer to form a plurality of conductive structures over the plurality of electrodes. Each of the plurality of conductive structures contacts a corresponding subset of the plurality of electrodes.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 6, 2025
    Inventors: Shu-Cheng Chin, Kong-Beng Thei
  • Patent number: D1071894
    Type: Grant
    Filed: August 28, 2023
    Date of Patent: April 22, 2025
    Assignee: Dell Products L.P.
    Inventors: Sok Hui Khoo, Shu-Cheng Wu, Ming Zhaozi