Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: A display apparatus includes a light-transmitting structural plate, some optical microscopic structures, an optical film, a base plate and some light emitting elements. The light-transmitting structural plate has a first side and a second side opposite to each other. The optical microscopic structures are regularly arrayed and formed on the first side or the second side. The optical microscopic structure has an inclined surface connecting at a connecting line and forming an angle ranging between 30 degrees and 150 degrees with a corresponding inclined surface of an adjacent one of the optical microscopic structures. The optical film is located on the first side. The base plate is separated from the second side by a space. The light emitting elements are located inside the space and disposed on the base plate. The light emitting elements respectively emit a light ray to the light-transmitting structural plate.

Abstract: A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.

Abstract: A manufacturing method of a flash memory comprising forming a patterned first dielectric layer, forming a patterned first conductive layer and a patterned hard mask layer on a substrate. Next, forming a conformal second conductive layer on the substrate, and etching back the second conductive layer by using the hard mask layer as a etching stop layer to form a conductive spacer on both of the sidewalls of the first conductive layer. Thereafter, removing the hard mask layer, and forming a second dielectric layer and a third conductive layer on the substrate. Finally, a stacked gate structure is constructed by the third conductive layer, the second dielectric layer, the first conductive layer, the conductive spacer and the first dielectric layer, in which a floating gate of the stacked gate structure is constructed by a remainer portion of the first conductive layer and the conductive spacer. And a source/drain region is formed in both sides of the stacked gate structure.

Abstract: A manufacturing method of a flash memory comprising forming a patterned first dielectric layer, forming a patterned first conductive layer and a patterned hard mask layer on a substrate. Next, forming a conformal second conductive layer on the substrate, and etching back the second conductive layer by using the hard mask layer as a etching stop layer to form a conductive spacer on both of the sidewalls of the first conductive layer. Thereafter, removing the hard mask layer, and forming a second dielectric layer and a third conductive layer on the substrate. Finally, a stacked gate structure is constructed by the third conductive layer, the second dielectric layer, the first conductive layer, the conductive spacer and the first dielectric layer, in which a floating gate of the stacked gate structure is constructed by a remainer portion of the first conductive layer and the conductive spacer. And a source/drain region is formed in both sides of the stacked gate structure.

Abstract: A method for fabricating a gate of a flash memory is described. A tunneling oxide layer, a first polysilicon layer and a silicon nitride layer are sequentially formed on a substrate. A photo-resist layer is formed on the silicon nitride layer and then the photo-resist layer, the silicon nitride layer, the polysilicon layer, the tunneling oxide layer and the substrate are patterned to form a plurality of trenches in the substrate. An active area defined by every two trenches is simultaneously formed. The photo-resist layer is removed. A plurality of shallow trench isolation (STI) structures is formed in the trenches by filling the trenches with silicon oxide up to the top of the silicon nitride layer. The top portion of the shallow trench isolation structures is removed to expose the sidewall of the silicon nitride layer and the top portion of the sidewall of the first polysilicon layer. Part of the silicon nitride layer is removed by wet etching.

Abstract: A method of forming the floating gate of a flash memory unit. A tunnel oxide layer and a first floating gate layer are sequentially formed over a substrate. The first floating gate layer, the tunnel oxide layer and the substrate are patterned to form an opening. A first dielectric layer is formed over the substrate and the interior of the opening but without completely filling the opening. A second dielectric layer is formed over the first dielectric layer so that the opening is completely filled. The second dielectric layer is planarized to expose the first dielectric layer. The first dielectric layer is removed to expose the first floating gate layer. A second floating gate layer is formed over the first floating gate layer. The second floating gate is planarized to expose the second dielectric layer.

Abstract: A method of forming the floating gate of a flash memory unit. A tunnel oxide layer and a first floating gate layer are sequentially formed over a substrate. The first floating gate layer, the tunnel oxide layer and the substrate are patterned to form an opening. A first dielectric layer is formed over the substrate and the interior of the opening but without completely filling the opening. A second dielectric layer is formed over the first dielectric layer so that the opening is completely filled. The second dielectric layer is planarized to expose the first dielectric layer. The first dielectric layer is removed to expose the first floating gate layer. A second floating gate layer is formed over the first floating gate layer. The second floating gate is planarized to expose the second dielectric layer.

Abstract: A method for fabricating a gate of a flash memory is described. A tunneling oxide layer, a first polysilicon layer and a silicon nitride layer are sequentially formed on a substrate. A photo-resist layer is formed on the silicon nitride layer and then the photo-resist layer, the silicon nitride layer, the polysilicon layer, the tunneling oxide layer and the substrate are patterned to form a plurality trenches in the substrate. An active area defined by every two trenches is simultaneously formed. The photo-resist layer is removed. A plurality of shallow trench isolation (STI) structures is formed in the trenches by filling the trenches with silicon oxide up to the top of the silicon nitride layer. The top portion of the shallow trench isolation structures is removed to expose the sidewall of the silicon nitride layer and the top portion of the sidewall of the first polysilicon layer. Part of the silicon nitride layer is removed by wet etching.