Patents by Inventor Shu-Cheng Lin

Shu-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250125309
    Abstract: Vertically stacked semiconductor devices and methods of fabrication thereof that include a first device structure bonded to a second device structure via bonding layers having compressible metal bonding structures. The compressible metal bonding structures may be fabricated using an electroless deposition (ED) process, and may be less dense with a greater degree of compressibility than equivalent materials deposited by related processes. Accordingly, mating pairs of metal bonding structures may have a degree of compliance that enables effective metal-to-metal contact during a subsequent bonding process. Recrystallization of the metal material during an annealing process may produce shrinkage of the metal material and the formation of void areas between the metal bonds and the surrounding dielectric layers, thereby reducing stress on the surrounding dielectric-to-dielectric interface.
    Type: Application
    Filed: October 11, 2023
    Publication date: April 17, 2025
    Inventors: Kai-Hsiang Yang, Chin-Fu Kao, Amram Eitan, Shu-Cheng Lin
  • Publication number: 20250014988
    Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes: forming a first metal structure in a first ILD layer; planarizing the first metal structure and the first ILD layer, wherein the planarizing generates a groove at an interface of the first metal structure and the first ILD layer; forming an ESL on the first metal structure and the first ILD layer; forming a second ILD layer on the ESL; performing a first etch to remove a portion of the second ILD layer to form a first opening; performing a second etch to remove a portion of the ESL through the opening; performing a third etch to remove a portion of the first ILD layer through the first opening to form a second opening in the first ILD layer; and enlarging the second opening to connected with the groove to form a contact hole.
    Type: Application
    Filed: July 7, 2023
    Publication date: January 9, 2025
    Inventors: SHU-CHENG LIN, SHIH YANG CHEN, TSUNG-YU CHIANG
  • Patent number: 10838806
    Abstract: A solid state storage system, and method of operation thereof, including: a system interface configured to receive host commands; a controller, coupled to the system interface, configured to identify frequently read data blocks from the host commands; a non-volatile memory, coupled to the controller, configured for access of the frequently read data blocks; an error correction code unit, coupled to the controller, configured to provide health monitor parameters for the frequently read data blocks verified by the controller; and a redundant frequently read data (RFRD) area, coupled to the error correction code unit, configured to transfer a recovered data from the frequently read data blocks.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: November 17, 2020
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Fong-Long Lin, Shu-Cheng Lin
  • Patent number: 10185609
    Abstract: Approaches, techniques, and mechanisms are disclosed for improving data retention using a virtual timer. A memory controller may use a raw bit error rate (RBER) to find an equivalent temperature-accelerated data age of a data item. The data age is computed by using the initial RBER of virtual timing data (VTD) as a virtual write in time of the data item compared to a present time using the current RBER of the VTD. When the data age is determined to exceed a data retention threshold, a data refresh is performed on the data item at the memory block on the memory device. The data age may be stored as virtual timing data on the memory block.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 22, 2019
    Assignee: SMART Modular Technologies, Inc.
    Inventor: Shu-Cheng Lin
  • Publication number: 20180232159
    Abstract: A solid state storage system, and method of operation thereof, including: a system interface configured to receive host commands; a controller, coupled to the system interface, configured to identify frequently read data blocks from the host commands; a non-volatile memory, coupled to the controller, configured for access of the frequently read data blocks; an error correction code unit, coupled to the controller, configured to provide health monitor parameters for the frequently read data blocks verified by the controller; and a redundant frequently read data (RFRD) area, coupled to the error correction code unit, configured to transfer a recovered data from the frequently read data blocks.
    Type: Application
    Filed: April 17, 2018
    Publication date: August 16, 2018
    Inventors: Fong-Long Lin, Shu-Cheng Lin
  • Publication number: 20180181454
    Abstract: Approaches, techniques, and mechanisms are disclosed for improving data retention using a virtual timer. A memory controller may use a raw bit error rate (RBER) to find an equivalent temperature-accelerated data age of a data item. The data age is computed by using the initial RBER of virtual timing data (VTD) as a virtual write in time of the data item compared to a present time using the current RBER of the VTD. When the data age is determined to exceed a data retention threshold, a data refresh is performed on the data item at the memory block on the memory device. The data age may be stored as virtual timing data on the memory block.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventor: Shu-Cheng Lin
  • Patent number: 9946469
    Abstract: A solid state storage system, and method of operation thereof, including: a system interface configured to receive host commands; a controller, coupled to the system interface, configured to identify frequently read data blocks from the host commands; a non-volatile memory, coupled to the controller, configured for access of the frequently read data blocks; an error correction code unit, coupled to the controller, configured to provide health monitor parameters for the frequently read data blocks verified by the controller; and a redundant frequently read data (RFRD) area, coupled to the error correction code unit, configured to transfer a recovered data from the frequently read data blocks.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: April 17, 2018
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Fong-Long Lin, Shu-Cheng Lin
  • Patent number: 9842768
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer and a first conductive structure over a substrate. The first dielectric layer surrounds the first conductive structure. The method includes forming a second dielectric layer over the first dielectric layer. The second dielectric layer has an opening exposing the first conductive structure. The method includes forming a seal layer over the first conductive structure and an inner wall of the opening. The seal layer is in direct contact with the first dielectric layer and the second dielectric layer, and the seal layer includes a dielectric material comprising an oxygen compound. The method includes removing the seal layer over the first conductive structure. The method includes filling a second conductive structure into the opening.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Cheng Lin, Chih-Lin Wang, Kang-Min Kuo
  • Publication number: 20170269852
    Abstract: A solid state storage system, and method of operation thereof, including: a system interface configured to receive host commands; a controller, coupled to the system interface, configured to identify frequently read data blocks from the host commands; a non-volatile memory, coupled to the controller, configured for access of the frequently read data blocks; an error correction code unit, coupled to the controller, configured to provide health monitor parameters for the frequently read data blocks verified by the controller; and a redundant frequently read data (RFRD) area, coupled to the error correction code unit, configured to transfer a recovered data from the frequently read data blocks.
    Type: Application
    Filed: March 21, 2016
    Publication date: September 21, 2017
    Inventors: Fong-Long Lin, Shu-Cheng Lin
  • Publication number: 20170221758
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer and a first conductive structure over a substrate. The first dielectric layer surrounds the first conductive structure. The method includes forming a second dielectric layer over the first dielectric layer. The second dielectric layer has an opening exposing the first conductive structure. The method includes forming a seal layer over the first conductive structure and an inner wall of the opening. The seal layer is in direct contact with the first dielectric layer and the second dielectric layer, and the seal layer includes a dielectric material comprising an oxygen compound. The method includes removing the seal layer over the first conductive structure. The method includes filling a second conductive structure into the opening.
    Type: Application
    Filed: April 18, 2017
    Publication date: August 3, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Cheng LIN, Chih-Lin WANG, Kang-Min KUO
  • Patent number: 9633941
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a seal layer covering an inner wall of the first opening and in direct contact with the first dielectric layer. The seal layer includes a dielectric material including an oxygen compound. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the seal layer. The second conductive structure is electrically connected to the first conductive structure.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Cheng Lin, Chih-Lin Wang, Kang-Min Kuo
  • Publication number: 20170053868
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a seal layer covering an inner wall of the first opening and in direct contact with the first dielectric layer. The seal layer includes a dielectric material including an oxygen compound. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the seal layer. The second conductive structure is electrically connected to the first conductive structure.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 23, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Cheng LIN, Chih-Lin WANG, Kang-Min KUO
  • Publication number: 20160035733
    Abstract: A NAND flash circuit structure includes two select gates disposed on a substrate, and an even number of spaced-apart word lines disposed between the two select gates. The select gate is provided with a first portion and a second portion. The thickness of the first portion and the second portion are different.
    Type: Application
    Filed: October 12, 2015
    Publication date: February 4, 2016
    Inventors: Shu-Cheng Lin, Zih-Song Wang, Yi-Shiang Chang
  • Patent number: 9196623
    Abstract: A semiconductor circuit structure and process of making the same is provided in the present invention, comprising the steps of providing a substrate having a target layer and a hard mask layer, forming a patterned small core body group and a large core body group on the hard mask layer, forming a spacer material layer conformally on the substrate and the core body groups, forming filling bodies in each recess of the spacer material layer, performing a first etching process to remove exposed spacer material layer, using the filling bodies as a mask to perform a second etching process for patterning the hard mask layer, and using the patterned hard mask layer as a mask to perform a third etching process for patterning the conductive layer.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: November 24, 2015
    Assignee: Powerchip Technology Corporation
    Inventors: Shu-Cheng Lin, Zih-Song Wang, Yi-Shiang Chang
  • Patent number: 8914877
    Abstract: A method for unlocking a handheld device with a touch screen includes accessing a social network using login information, acquiring information of a plurality of friends from the social network. The method further includes creating an unlocking interface on the touch screen according to a second amount of a secondary key based on the plurality of friends and a question based on the first amount of a primary key based on the plurality of friends. An input event of a user on the unlocking interface is detected the handheld device is transitioned from a lock state to an unlock state upon the condition that the input event corresponds to a correct answer.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: December 16, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Shu-Cheng Lin, Chun-Wei Kuo
  • Patent number: 8883636
    Abstract: A semiconductor process for forming specific pattern features comprising the steps of forming a target layer, a hard mask layer and a plurality of equally spaced-apart core bodies on a substrate, forming spacers on sidewalls of the core bodies, removing the core bodies so that the spacers are spaced-apart on the hard mask layer, using spacers as a mask to pattern the hard mask layer, removing the hard mask bodies outside of a predetermined region, forming photoresists on several outermost hard mask bodies of the predetermined region, and using the photoresists and remaining hard mask bodies as a mask to pattern the target layer.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: November 11, 2014
    Assignee: Powerchip Technology Corporation
    Inventors: Zih-Song Wang, Shu-Cheng Lin, Yoshikazu Miyawaki
  • Publication number: 20140053258
    Abstract: A method for unlocking a handheld device with a touch screen includes accessing a social network using login information, acquiring information of a plurality of friends from the social network. The method further includes creating an unlocking interface on the touch screen according to a second amount of a secondary key based on the plurality of friends and a question based on the first amount of a primary key based on the plurality of friends. An input event of a user on the unlocking interface is detected the handheld device is transitioned from a lock state to an unlock state upon the condition that the input event corresponds to a correct answer.
    Type: Application
    Filed: May 6, 2013
    Publication date: February 20, 2014
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: SHU-CHENG LIN, CHUN-WEI KUO
  • Publication number: 20130264622
    Abstract: A semiconductor circuit structure and process of making the same is provided in the present invention, comprising the steps of providing a substrate having a target layer and a hard mask layer, forming a patterned small core body group and a large core body group on the hard mask layer, forming a spacer material layer conformally on the substrate and the core body groups, forming filling bodies in each recess of the spacer material layer, performing a first etching process to remove exposed spacer material layer, using the filling bodies as a mask to perform a second etching process for patterning the hard mask layer, and using the patterned hard mask layer as a mask to perform a third etching process for patterning the conductive layer.
    Type: Application
    Filed: September 5, 2012
    Publication date: October 10, 2013
    Inventors: Shu-Cheng Lin, Zih-Song Wang, Yi-Shiang Chang
  • Publication number: 20130260557
    Abstract: A semiconductor process for forming specific pattern features comprising the steps of forming a target layer, a hard mask layer and a plurality of equally spaced-apart core bodies on a substrate, forming spacers on sidewalls of the core bodies, removing the core bodies so that the spacers are spaced-apart on the hard mask layer, using spacers as a mask to pattern the hard mask layer, removing the hard mask bodies outside of a predetermined region, forming photoresists on several outermost hard mask bodies of the predetermined region, and using the photoresists and remaining hard mask bodies as a mask to pattern the target layer.
    Type: Application
    Filed: September 12, 2012
    Publication date: October 3, 2013
    Inventors: Zih-Song Wang, Shu-Cheng Lin, Yoshikazu Miyawaki
  • Publication number: 20130140662
    Abstract: A method for forming the photodiode device is provided. The method comprises providing a substrate, then a transparent conductive film is formed on the substrate. A conductive polymer is formed on the transparent conductive film. A photoactive layer is formed on the conductive polymer. A charge blocking layer is formed on the photoactive layer. Finally, a cathode metal is formed on the charge blocking layer.
    Type: Application
    Filed: May 8, 2012
    Publication date: June 6, 2013
    Applicant: National Chiao Tung University
    Inventors: Fang-Chung Chen, Shu-Cheng Lin