Abstract: An electronic device includes a flexible substrate and a conductive wire. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. The metal portion includes a plurality of extending portions and a plurality of joint portions, and each of the openings is surrounded by two of the plurality of extending portions and two of the plurality of joint portions. A ratio of a sum of widths of the plurality of extending portions to a sum of widths of the plurality of joint portions is in a range from 0.8 to 1.2.

Abstract: A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.

Abstract: Disclosed is an electronic device having a display region and a peripheral region adjacent to the display region. The electronic device includes a first electrode disposed in the display region, a second electrode disposed in the display region, a circuit module disposed in the peripheral region, a first electrical trace, and a second electrical trace electrically insulated from the first electrical trace. The circuit module is electrically connected to the first electrode through the first electrical trace and provides a first driving voltage to the first electrical trace. The circuit module is electrically connected to the second electrode through the second electrical trace and provides a second driving voltage to the second electrical trace, and the first driving voltage is different from the second driving voltage. In a top view, the first electrical trace at least partially overlaps the second electrical trace.

Abstract: Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.

Abstract: Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.

Abstract: A method for etching a pattern within a dual-layer stack dielectric layer employed within a microelectronics fabrication. A first low dielectric constant dielectric layer employing HSQ polymer spin-on-glass (SOP) dielectric material is formed over a substrate. A second dielectric layer is then provided to form a dual level dielectric stack layer. There is then formed over the dual dielectric layer a patterned photoresist etch mask layer. The pattern is transferred into and through the dielectric stack layer employing an anisotropic reactive ion etching environment to etch the pattern through the patterned photoresist etch mask layer. There is then added to the etchant environment additional gases under conditions to form a plasma in the final etching environment to stabilize the etched pattern surface and attenuate degradation of the etched pattern during subsequent stripping of the photoresist etch mask pattern.

Abstract: Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.

Abstract: A method for etching polysilicon or polycide gate electrodes over thin gate oxides is described wherein the problem of pitting and trenching of the silicon beneath the gate oxide, caused by penetration of the polysilicon etchant through the gate oxide is resolved. A cause of gate oxide penetration is found to be a native oxide formed on the exposed surface of polycide or polysilicon gate layer. The native oxide is uneven and has local thin spots which are penetrated by the traditional polysilicon etchants. The erratic penetration of the native oxide produces an uneven etch front which propagates down to the gate oxide. Gate oxides thinner than about 125 .ANG. are incapable of absorbing this irregularity during polysilicon over etch and are penetrated causing deep pockets in the subjacent silicon. The novel method first etches the native oxide with a brief highly selective fluorocarbon etch and then etches through the polycide or polysilicon with C.2 and HBr to endpoint on the thin gate oxide.

Abstract: A method for forming a patterned layer within an integrated circuit. There is first provided a substrate having formed thereupon a blanket target layer. Formed upon the blanket target layer is a blanket focusing layer, where the blanket focusing layer is formed from an organic material and where the blanket focusing layer is susceptible to a reproducible negative etch bias within a first etch method employed in etching the blanket focusing layer to form a patterned focusing layer. There is then formed upon the blanket focusing layer a blanket photoresist layer which is photoexposed and developed to form a patterned photoresist layer. There is then etched through the first etch method the blanket focusing layer to form the patterned focusing layer while employing the patterned photoresist layer as a first etch mask layer. The patterned focusing layer so formed has the reproducible negative etch bias with respect to the patterned photoresist layer.