Patents by Inventor Shu-Ching TSAI

Shu-Ching TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10756625
    Abstract: An integrated module of acoustic wave device with active thermal compensation comprises a substrate, an acoustic wave filter, an active adjustment circuit and at least one variable capacitance device. The acoustic wave filter comprises a plurality of series acoustic wave resonators formed on the substrate, at least one shunt acoustic wave resonator formed on the substrate and a thermal sensing acoustic wave resonator. Each of the variable capacitance device is connected in parallel to one of the series and shunt acoustic wave resonators. The active adjustment circuit outputs an active thermal compensation signal correlated to a thermal variation sensed by the thermal sensing acoustic wave resonator to the variable capacitance device. The active thermal compensation signal induces a capacitance variation of the variable capacitance device such that the impact of the thermal variation to the acoustic wave device is compensated.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: August 25, 2020
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Re Ching Lin, Shu Hsiao Tsai, Cheng Kuo Lin, Chih-Feng Chiang, Fan Hsiu Huang, Tung-Yao Chou
  • Patent number: 10727741
    Abstract: An acoustic wave filter having thermal sensing acoustic wave resonator comprises a substrate, a plurality of series acoustic wave resonators formed on the substrate, at least one shunt acoustic wave resonator formed on the substrate and a thermal sensing acoustic wave resonator. The thermal sensing acoustic wave resonator is one of a series acoustic wave resonator and a shunt acoustic wave resonator. Thereby the thermal sensing acoustic wave resonator plays dual roles of thermal sensing and acoustic wave filtering.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: July 28, 2020
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Re Ching Lin, Shu Hsiao Tsai, Cheng Kuo Lin, Fan Hsiu Huang, Chih-Feng Chiang, Tung-Yao Chou
  • Patent number: 10651296
    Abstract: Methods of fabricating FinFET devices are provided. The method includes forming a fin over a substrate. The method also includes implanting a first dopant on a top surface of the fin and implanting a second dopant on a sidewall surface of the fin. The first dopant is different from the second dopant. The method further includes forming an oxide layer on the top surface and the sidewall surface of the fin, and forming a gate electrode layer over the oxide layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Han Wu, Tong-Min Weng, Chun-Yi Huang, Po-Ching Lee, Chih-Hsuan Hsieh, Shu-Ching Tsai
  • Patent number: 10593246
    Abstract: A pixel array substrate includes a substrate, first and second scan lines, data lines, and pixel structures. The first and second scan lines are disposed alternately and are enabled for different time durations in the same frame time. The data lines intersect with the first and second scan lines. Each of the pixel structures includes first and second active devices, and a pixel electrode. The first and second active devices are turned on and off by the first and second scan lines, respectively. The pixel electrode is connected to the first active device which is connected to one of the data lines by being connected to the second active device. A distance between the first and second scan lines adjacent to each other is a third to a half of a pitch of the pixel structures.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: March 17, 2020
    Assignee: E Ink Holdings Inc.
    Inventors: Shu-Fen Tsai, Jia-Hung Chen, Kuang-Heng Liang, Chih-Ching Wang, Ian French
  • Publication number: 20200058557
    Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 20, 2020
    Inventors: Ya-Yi Tsai, Yi-Hsuan Hsiao, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
  • Publication number: 20200035815
    Abstract: Methods of fabricating FinFET devices are provided. The method includes forming a fin over a substrate. The method also includes implanting a first dopant on a top surface of the fin and implanting a second dopant on a sidewall surface of the fin. The first dopant is different from the second dopant. The method further includes forming an oxide layer on the top surface and the sidewall surface of the fin, and forming a gate electrode layer over the oxide layer.
    Type: Application
    Filed: July 30, 2018
    Publication date: January 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Han WU, Tong-Min WENG, Chun-Yi HUANG, Po-Ching LEE, Chih-Hsuan HSIEH, Shu-Ching TSAI
  • Patent number: 10535654
    Abstract: A semiconductor device includes a substrate, first and second fins protruding out of the substrate, and first and second high-k metal gates (HK MG) disposed over the first and second fins, respectively. From a top view, the first and second fins are arranged lengthwise along a first direction, the first and second HK MG are arranged lengthwise along a second direction generally perpendicular to the first direction, and the first and second HK MG are aligned along the second direction. In a cross-sectional view cut along the second direction, the first HK MG has a first sidewall that is slanted from top to bottom towards the second HK MG, and the second HK MG has a second sidewall that is slanted from top to bottom towards the first HK MG. Methods for producing the semiconductor device are also disclosed.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Yi Tsai, Chun-Liang Lai, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
  • Patent number: 10498310
    Abstract: A protective cover for an acoustic wave device and a fabrication method thereof, for protecting an acoustic wave device having a resonant area during a packaging operation so as to avoid molding compound flowing onto the resonant area of the acoustic wave device. The fabrication method comprises: defining a sacrificial area on the acoustic wave device; forming a sacrificial layer on the sacrificial area; covering a metal covering layer on the sacrificial layer and connecting a bottom rim of the metal covering layer to the acoustic wave device and forming an opening between the bottom rim of the metal covering layer and the acoustic wave device; and removing the sacrificial layer to form a cavity between the metal covering layer and the resonant area by using a chemical solution, wherein the chemical solution enters from the opening between the metal covering layer and the acoustic wave device.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: December 3, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Cheng-Kuo Lin, Shu-Hsiao Tsai, Rong-Hao Syu, Yi-Ling Liu, Re-Ching Lin, Pei-Chun Liao
  • Patent number: 10460994
    Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Yi Tsai, Yi-Hsuan Hsiao, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
  • Patent number: 10453805
    Abstract: A chip stack having a protection structure for semiconductor device package, which comprises a first chip and a second chip stacked with each other, wherein said first chip has a first surface, said second chip has a second surface, said first surface and said second surface are two surfaces facing to each other, wherein at least one metal pillar is formed on at least one of said first surface and said second surface and connected with the other, at least one protection ring is formed on at least one of said first surface and said second surface and having a first gap with the other, and at least one electrical device is formed on at least one of said first surface and said second surface, wherein said at least one electrical device is located inside at least one of said at least one protection ring.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: October 22, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Pei-Chun Liao, Po-Wei Ting, Chih-Feng Chiang, Yu-Kai Wu, Yu-Fan Chang, Re-Ching Lin, Shu-Hsiao Tsai, Cheng-Kuo Lin
  • Publication number: 20190164839
    Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.
    Type: Application
    Filed: March 28, 2018
    Publication date: May 30, 2019
    Inventors: Ya-Yi Tsai, Yi-Hsuan Hsiao, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
  • Patent number: 10298203
    Abstract: A chip stack having a protection structure for semiconductor device package comprises a first chip and a second chip stacked with each other. A first surface of the first chip and a second surface of the second chip are facing to each other. At least one metal pillar is formed on at least one of the first surface and the second surface and connected with the other. At least one protection ring is formed on at least one of the first surface and the second surface and having a first gap with the other. At least one electrical device is formed on at least one of the first surface and the second surface and is located inside at least one of the at least one protection ring, wherein the at least one electrical device includes a temperature sensor.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 21, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Pei-Chun Liao, Po-Wei Ting, Chih-Feng Chiang, Yu-Kai Wu, Yu-Fan Chang, Re-Ching Lin, Shu-Hsiao Tsai, Cheng-Kuo Lin
  • Publication number: 20190139476
    Abstract: A pixel array substrate includes a substrate, first and second scan lines, data lines, and pixel structures. The first and second scan lines are disposed alternately and are enabled for different time durations in the same frame time. The data lines intersect with the first and second scan lines. Each of the pixel structures includes first and second active devices, and a pixel electrode. The first and second active devices are turned on and off by the first and second scan lines, respectively. The pixel electrode is connected to the first active device which is connected to one of the data lines by being connected to the second active device. A distance between the first and second scan lines adjacent to each other is a third to a half of a pitch of the pixel structures.
    Type: Application
    Filed: September 14, 2018
    Publication date: May 9, 2019
    Applicant: E Ink Holdings Inc.
    Inventors: Shu-Fen Tsai, Jia-Hung Chen, Kuang-Heng Liang, Chih-Ching Wang, Ian French