Abstract: A method of noise mitigation in a multi-carrier communication system includes receiving a signal from a decision device, determining whether synchronization symbol update is enabled, updating at least one of frequency-domain equalizer (FEQ) coefficients or digital echo canceller (DEC) coefficients in synchronization symbol periods if the synchronization symbol update is enabled, determining whether data symbol update is performed if the synchronization symbol update is not enabled, determining whether a flag associated with the signal is set if the data symbol update is not performed, and updating at least one of FEQ or DEC coefficients associated with the signal in synchronization symbol periods if the flag is set.

Abstract: An apparatus for noise mitigation in a multi-carrier communication system includes a filter to receive a signal from an analog front end, a time-domain equalizer (TEQ) coupled with the filter, a fast Fourier transform (FFT) module, a frequency-domain equalizer (FEQ) coupled with the FFT module, a slicer to serve as a decision device, and a controller to calculate a power of signal at at least one of an input of the filter, an input of the TEQ, an output of the TEQ, an output of the FFT module, an output of the FEQ or an output of the slicer and compare at least one of the power of the at least one signal with a respective threshold so as to determine whether impulse noise occurs, wherein the controller is configured to disable adaptation of system parameters in at least one of the FEQ, a phase-lock loop (PLL) or a digital echo canceller (DEC) when impulse noise is detected.

Abstract: A method of noise mitigation in a multi-carrier communication system includes receiving a signal from a decision device, determining whether synchronization symbol update is enabled, updating at least one of frequency-domain equalizer (FEQ) coefficients or digital echo canceller (DEC) coefficients in synchronization symbol periods if the synchronization symbol update is enabled, determining whether data symbol update is performed if the synchronization symbol update is not enabled, determining whether a flag associated with the signal is set if the data symbol update is not performed, and updating at least one of FEQ or DEC coefficients associated with the signal in synchronization symbol periods if the flag is set.

Abstract: An all-digital phase-locked loop (ADPLL) device includes a primary ADPLL circuit and a controller which allow an in-phase output signal to be generated even when the incoming reference signal is lost. The primary ADPLL loop includes a phase detector, a digital loop filter, a first digital control oscillator (DCO) for generating a loop signal which is phase-locked to a received reference signal, and a frequency divider. The controller generates control signals to be used by a secondary DCO or the first DCO to generate a synchronized system output signal. The controller includes an accumulator which accumulates the number of phase-hopping events performed by the first DCO for a certain time period, a first-in-first-out (FIFO) buffer which stores a number of consecutive phase-hopping samples from the accumulator, and a calculator for determining an average of the consecutive values stored in the FIFO buffer.

Abstract: An improved high-frequency all-digital phase-locked loop for locking a local signal in phase with an input signal is disclosed. It contains a novel digital control oscillator which includes: (a) a delay line comprising L delay gates for generating L clocks, where L is an integer and each of the delay gates has a delay time .PHI.; (b) a programmable up-down N-counter, where N is an integer; (c) a multiplexer which selects one of the L clocks based on a count of the up-down N-counter programmable; and (d) an adaptive-compensative circuit for determining the value of N based on the following conditions: ##EQU1## The adaptive-compensative circuit is implemented with a boolean encoder. This improved design allows all-digital PLL's to be constructed without a high frequency system clock, while, at the same time, maintains excellent stability and generates minimum output jitters.