Abstract: Provided is a monoclonal antibody of matrix metalloproteinase 1. The monoclonal antibody has a heavy chain variable region with an amino sequence comprising i) CDR1 selected from the group consisting of SEQ ID NOs: 1, 7 and 13, ii) CDR2 selected from the group consisting of SEQ ID NOs: 2, 8 and 14, and iii) CDR3 selected from the group consisting of SEQ ID NOs: 3, 9 and 15. The monoclonal antibody also has a light chain variable region with an amino sequence comprising i) CDR1 selected from the group consisting of SEQ ID NOs: 4, 10 and 16, ii) CDR2 selected from the group consisting of SEQ ID NOs: to 5, 11 and 17, and iii) CDR3 selected from the group consisting of SEQ ID NOs: 6, 12 and 18. A polynucleotide encoding the monoclonal antibody and a complementary polynucleotide sequence thereof are provided as well. A detection kit and a detection method are also provided, wherein the detection kit contains the monoclonal antibody of the matrix metalloproteinase 1.

Abstract: A clock frequency divider circuit and method of dividing a clock frequency are provided. The clock frequency divider circuit includes a first flip-flop circuit, a second flip-flop circuit, a third flip-flop circuit, a first logic control unit and a second logic control unit, wherein the first flip-flop circuit has two clock input terminals connected to the second and third flip-flop circuits respectively and two control signal input terminals connected to the first and second logic control units respectively. The second and third flip-flop circuits count rising edges and falling edges of an input frequency under control of the first and second flip-flop circuits and accordingly, symmetric output signals are output from the first flip-flop circuit.

Abstract: A pulse generator comprises a CMOS inverter, a capacitive device and a resistive device, where the CMOS inverter has two terminals connected to a source voltage and a reference voltage, e.g., ground, respectively, the capacitor device and the resistive device are connected to the input end of CMOS inverter, and pulses are generated at the output end of the CMOS inverter. The capacitive device is charged by a boost signal and discharged through the resistive device, so as to manipulate a potential at the input end of the CMOS inverter to control the operations of the transistors included in the CMOS inverter, thereby changing the level of the output voltage of the CMOS inverter. The widths of the pulses can be adjustable by a control signal received by the resistive device.

Abstract: A clock frequency divider circuit and method of dividing a clock frequency are provided. The clock frequency divider circuit includes a first flip-flop circuit, a second flip-flop circuit, a third flip-flop circuit, a first logic control unit and a second logic control unit, wherein the first flip-flop circuit has two clock input terminals connected to the second and third flip-flop circuits respectively and two control signal input terminals connected to the first and second logic control units respectively. The second and third flip-flop circuits count rising edges and falling edges of an input frequency under control of the first and second flip-flop circuits and accordingly, symmetric output signals are output from the first flip-flop circuit.

Abstract: In this invention is described an electrically programmable fuse that uses a floating gate to control the fuse action. The activation of the fuse can be done at any time during the life of the product containing the fuse. By programming a charge onto the floating gate an active transistor is made to conduct or not to conduct. The fuse can be reused by re-programming the fuse to the previous state. Different states of the fuse which represent product options can be obtained by programming appropriate voltage levels.

Abstract: In this invention is described an electrically programmable fuse that uses a floating gate to control the fuse action. The activation of the fuse can be done at any time during the life of the product containing the fuse. By programming a charge onto the floating gate an active transistor is made to conduct or not to conduct. The fuse can be reused by re-programming the fuse to the previous state. Different states of the fuse which represent product options can be obtained by programming appropriate voltage levels.

Abstract: A new method for fabricating a reversed MOS structure in order to provide latchup immunity in the manufacture of integrated circuits is described. An active area is provided in a semiconductor substrate separated from other active areas by isolation regions. A dielectric layer is formed on the surface of the semiconductor substrate in the active area. A polysilicon layer is deposited overlying the dielectric layer and patterned. A mask is formed over a portion of the polysilicon layer in the active area. Ions are implanted into the polysilicon layer not covered by the mask to form implanted regions within the polysilicon layer and simultaneously form implanted regions within the substrate adjacent to the polysilicon layer wherein the implanted regions in the polysilicon layer form source and drain regions and wherein the polysilicon layer covered by the mask forms a channel region and wherein the implanted regions within the substrate diffuse together to form a gate electrode underlying the channel region.

Abstract: In this invention is described an electrically programmable fuse that uses a floating gate to control the fuse action. The activation of the fuse can be done at any time during the life of the product containing the fuse. By programming a charge onto the floating gate an active transistor is made to conduct or not to conduct. The fuse can be reused by re-programming the fuse to the previous state. Different states of the fuse which represent product options can be obtained by programming appropriate voltage levels.