Abstract: A quick dispatching rule screening method and apparatus are provided. The quick dispatching rule screening method includes following steps. A scheduling result and a corresponding scenario are obtained. A dispatching rule mining table is established according to the scheduling result, where the dispatching rule mining table includes a dispatching rule and an operation. A participation rate of each dispatching rule in the dispatching rule mining table is calculated. A contribution rate is calculated according to the participation rate to obtain a filter value. A selected dispatching rule is decided according to the filter value.

Abstract: A parameter optimization device includes a data acquisition module, a sampling function calculation module, a clustering module and a parameter recommendation module. The data acquisition module is configured to acquire several input parameter values and corresponding several measurement output values. The sampling function calculation module is configured to obtain several sampling function values according to the input parameter values and the measurement output values. The clustering module is configured to obtain several parameter groups according to the input parameter values and the sampling function values. The parameter recommendation module is configured to obtain several recommended parameter values from at least one of the parameter groups.

Abstract: A quick dispatching rule screening method and apparatus are provided. The quick dispatching rule screening method includes following steps. A scheduling result and a corresponding scenario are obtained. A dispatching rule mining table is established according to the scheduling result, where the dispatching rule mining table includes a dispatching rule and an operation. A participation rate of each dispatching rule in the dispatching rule mining table is calculated. A contribution rate is calculated according to the participation rate to obtain a filter value. A selected dispatching rule is decided according to the filter value.

Abstract: A device for harvesting and managing wireless energy includes a wireless receiver, a first rectifier, a first capacitor, a voltage detection circuit, a first electrical switch, a second rectifier and a second capacitor connected to each other. The wireless receiver receives a wireless RF signal and converts it into an AC voltage with an input power. The first rectifier receives the AC voltage, converts it into a first DC voltage and transmits the first DC voltage to a load. The voltage detection circuit has a threshold voltage value and detects the first DC voltage. When the first DC voltage is larger than the threshold voltage value, the voltage detection circuit turns on the first electrical switch and the second rectifier receives the AC voltage through the first electrical switch to share the input power received by the first rectifier, thereby achieving the high energy conversion efficiency.

Abstract: A mobile carrier includes a first frame, a directional wheel pivoted to the first frame, a second frame pivoted to the first frame, a steering adjustment mechanism connected to the second frame, and a steering wheel. The steering adjustment mechanism includes a first rotating element and a second rotating element coupled to the first rotating element. When a first rotating axis of the first rotating element is perpendicular to a plane, the first and the second rotating elements are locked to each other and are capable of rotating around the first rotating axis simultaneously. When a second rotating axis of the second rotating element is perpendicular to the plane, rotational degree of freedom of the first rotating element is restricted, and the second rotating element is capable of rotating around the second rotating axis relative to the first rotating element. A steering adjustment mechanism is also provided.

Abstract: A mobile carrier includes a first frame, a directional wheel pivoted to the first frame, a second frame pivoted to the first frame, a steering adjustment mechanism connected to the second frame, and a steering wheel. The steering adjustment mechanism includes a first rotating element and a second rotating element coupled to the first rotating element. When a first rotating axis of the first rotating element is perpendicular to a plane, the first and the second rotating elements are locked to each other and are capable of rotating around the first rotating axis simultaneously. When a second rotating axis of the second rotating element is perpendicular to the plane, rotational degree of freedom of the first rotating element is restricted, and the second rotating element is capable of rotating around the second rotating axis relative to the first rotating element. A steering adjustment mechanism is also provided.

Abstract: A device for harvesting and managing wireless energy includes a wireless receiver, a first rectifier, a first capacitor, a voltage detection circuit, a first electrical switch, a second rectifier and a second capacitor connected to each other. The wireless receiver receives a wireless RF signal and converts it into an AC voltage with an input power. The first rectifier receives the AC voltage, converts it into a first DC voltage and transmits the first DC voltage to a load. The voltage detection circuit has a threshold voltage value and detects the first DC voltage. When the first DC voltage is larger than the threshold voltage value, the voltage detection circuit turns on the first electrical switch and the second rectifier receives the AC voltage through the first electrical switch to share the input power received by the first rectifier, thereby achieving the high energy conversion efficiency.

Abstract: A sense amplifier circuit includes a single-ended sense amplifier and an isolation switch. The isolation switch is coupled between a bias node and a first line of a memory device, receives an output of the single-ended sense amplifier and selectively isolates the bias node and the first line in response to the output of the single-ended sense amplifier. The first line is coupled to a plurality of memory cells of the memory device.

Abstract: A sense amplifier circuit includes a single-ended sense amplifier and an isolation switch. The isolation switch is coupled between a bias node and a first line of a memory device, receives an output of the single-ended sense amplifier and selectively isolates the bias node and the first line in response to the output of the single-ended sense amplifier. The first line is coupled to a plurality of memory cells of the memory device.

Abstract: A memory device includes a first signal line; a memory cell array divided into a first area and a second area and having a plurality of first memory cells and second memory cells in the first area and second area, respectively. The plurality of first and second memory cells are coupled the first signal line, and each has a reference node. A first voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of first memory cells, wherein the first voltage adjustments circuit includes: a first switch coupled between the reference nodes of the plurality of first memory cells and the ground, controlled by an address signal; and a first bias element coupled to the reference nodes of the plurality of first memory cells. A second voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of second memory cells.

Abstract: A memory device includes a first signal line; a memory cell array divided into a first area and a second area and having a plurality of first memory cells and second memory cells in the first area and second area, respectively. The plurality of first and second memory cells are coupled the first signal line, and each has a reference node. A first voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of first memory cells, wherein the first voltage adjustments circuit includes: a first switch coupled between the reference nodes of the plurality of first memory cells and the ground, controlled by an address signal; and a first bias element coupled to the reference nodes of the plurality of first memory cells. A second voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of second memory cells.

Abstract: A memory device is provided. The memory device includes a first signal line, a memory cell array, first and second voltage adjustment circuits. The memory cell array is divided into first and second areas and includes first memory cells in the first area and second memory cells in the second area. The first and second memory cells are coupled the first signal line. Each of the first and second memory cells has a reference node. The first voltage adjustment circuit adjusts voltages at the reference nodes of the first memory cells. The second voltage adjustment circuit adjusts voltages at the reference nodes of the second memory cells. The reference nodes of the first memory cells are coupled to a ground through the first voltage adjustment circuit. The reference nodes of the second memory cells are coupled to the ground through the second voltage adjustment circuit.

Abstract: An embodiment of the invention provides a binary CAM cell. The binary CAM cell includes a storage circuit, a first discharging circuit, and a second discharging circuit. The storage circuit is configured to provide a first stored bit and a second stored bit, which are complimentary bits of each other. The first discharging circuit is configured to either discharge or not discharge a match line according to the first stored bit provided by the storage circuit and a first searched bit provided by a first search line. The first discharging circuit includes a first PMOS transistor. The second discharging circuit is configured to either discharge or not discharge the match line according to the second stored bit provided by the storage circuit and a second searched bit provided by a second search line. The second discharging circuit includes a second PMOS transistor.

Abstract: A memory device is provided. The memory device includes a first signal line, a memory cell array, first and second voltage adjustment circuits. The memory cell array is divided into first and second areas and includes first memory cells in the first area and second memory cells in the second area. The first and second memory cells are coupled the first signal line. Each of the first and second memory cells has a reference node. The first voltage adjustment circuit adjusts voltages at the reference nodes of the first memory cells. The second voltage adjustment circuit adjusts voltages at the reference nodes of the second memory cells. The reference nodes of the first memory cells are coupled to a ground through the first voltage adjustment circuit. The reference nodes of the second memory cells are coupled to the ground through the second voltage adjustment circuit.

Abstract: Methods for determining the state of memory cells include using an asymmetric sense amplifier. The methods include sensing the voltages on bit line (BL) and bit line bar (BLB) signals by coupling the BL to a first output node of an imbalanced cross-coupled latch (ICL), the ICL outputting a logic low value if the a difference between the a voltage on the BL and a voltage on the BLB exceeds a threshold. Sensing the voltages includes providing at least a first and a second pull down field effect transistor (FET) each having a channel coupled between the first and second output nodes and a ground node, respectively, in a cross coupled arrangement, wherein the second pull down FET has a channel width that is greater than a channel width of the first pull down FET. Additional methods are disclosed.

Abstract: Methods for determining the state of memory cells include using an asymmetric sense amplifier. The methods include sensing the voltages on bit line (BL) and bit line bar (BLB) signals by coupling the BL to a first output node of an imbalanced cross-coupled latch (ICL), the ICL outputting a logic low value if the a difference between the a voltage on the BL and a voltage on the BLB exceeds a threshold. Sensing the voltages includes providing at least a first and a second pull down field effect transistor (FET) each having a channel coupled between the first and second output nodes and a ground node, respectively, in a cross coupled arrangement, wherein the second pull down FET has a channel width that is greater than a channel width of the first pull down FET. Additional methods are disclosed.

Abstract: Sensing circuits for determining the state of memory cells include a sense amplifier. The sense amplifier includes an imbalanced cross-coupled latch (ICL), a first gate field effect transistor (FET) between a bit line (BL) and a first output node, and a second gate FET between a bit line inverse (BLB) and a second output node. The ICL includes a first pull down FET between the first output node and an enable FET connected to electrical ground, and a second pull down FET between the second output node and the enable FET. Channel widths of the second pull down FET and the second gate FET are greater than channel widths of the first pull down FET and the first gate FET to enhance the ability to detect a one (1) and a zero (0) stored in a memory cell connected to the sense amplifier.

Abstract: Sensing circuits for determining the state of memory cells include a sense amplifier. The sense amplifier includes an imbalanced cross-coupled latch (ICL), a first gate field effect transistor (FET) between a bit line (BL) and a first output node, and a second gate FET between a bit line inverse (BLB) and a second output node. The ICL includes a first pull down FET between the first output node and an enable FET connected to electrical ground, and a second pull down FET between the second output node and the enable FET. Channel widths of the second pull down FET and the second gate FET are greater than channel widths of the first pull down FET and the first gate FET to enhance the ability to detect a one (1) and a zero (0) stored in a memory cell connected to the sense amplifier.

Abstract: An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.

Abstract: An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.