Abstract: A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.

Abstract: Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.

Abstract: An organometallic complex, a catalyst composition employing the same, and a method for preparing polyolefin are provided. The organometallic compound has a structure represented by Formula (I) wherein M is Ti, Zr, or Hf; X is —O—, or —NR6—; R1 and R2 are independently hydrogen, C1-6 alkyl group, C6-12 aryl group, or R1 and R2 are combined with the carbon atoms, to which they are attached, to form an C6-12 aryl moiety; R3, R4 and R5 are independently fluoride, chloride, bromide, C1-6 alkyl group, C6-12 aryl group, C3-6 hetero aryl group, C7-13 aryl alkyl group or C7-12 alkyl aryl group; and R6 is hydrogen, C6-12 aryl group or C7-12 alkyl aryl group.

Abstract: A semiconductor package is provided, which includes a first chip disposed over a first package substrate, a molding compound surrounding the first chip, a first thermal interface material disposed over the first chip and the molding compound, a heat spreader disposed over the thermal interface material, and a second thermal interface material disposed over the heat spreader. The first thermal interface material and the second thermal interface material have an identical width.

Abstract: The present invention provides a method of reducing nitrate content in a plant by supplementing Rhodopseudomonas palustris DSM 29314 with a hydroponic nutrient solution, wherein the plant can grow in the hydroponic nutrient solution. The bacteria can effectively reduce 50% to 88% of the nitrate content in the plant, and only requires half concentration of the hydroponic nutrient solution than usual to enhance the fresh and dry weight of the plant up to 17% to 44%. It can effectively reduce cost, increase income and provide safe crops.

Abstract: The present invention provides a method of reducing nitrate content in a plant by supplementing Rhodopseudomonas palustris DSM 29314 with a hydroponic nutrient solution, wherein the plant can grow in the hydroponic nutrient solution. The bacteria can effectively reduce 50% to 88% of the nitrate content in the plant, and only requires half concentration of the hydroponic nutrient solution than usual to enhance the fresh and dry weight of the plant up to 17% to 44%. It can effectively reduce cost, increase income and provide safe crops.

Abstract: An electronic device includes a multi-layer circuit board, a main antenna, and an electronic element. The multi-layer circuit board includes an outer layer, a ground layer, and a plurality of vias defined therein electrically connected the outer layer and the ground layer. The main antenna is mounted on the outer layer and electrically connected to the ground layer by the vias. The electronic element is mounted on the outer layer, soldered on the main antenna, and electrically connected to the ground layer by the main antenna.

Abstract: An electronic device includes a multi-layer circuit board, a main antenna, and an electronic element. The multi-layer circuit board includes an outer layer, a ground layer, and a plurality of vias defined therein electrically connected the outer layer and the ground layer. The main antenna is mounted on the outer layer and electrically connected to the ground layer by the vias. The electronic element is mounted on the outer layer, soldered on the main antenna, and electrically connected to the ground layer by the main antenna.