Abstract: The present invention provides a sputtering target having alarm function. The sputtering target comprises: a target body including a target material and having a bonding plane; a backing body bonded with the bonding plane of the target body; and at least one alarm body embedded in the target body. Wherein, a length of each alarm body, ratios of an area of each alarm body and the sum of area(s) of the at least one alarm body projected onto the bonding plane relative to an area of the bonding plane are controlled in a suitable range. Thus, the bonding strength and the heat-removing efficiency of the sputtering target can be maintained, and the distinguishable material of the alarm body can evolve a gas component distinguishable from a sputtering environment serving as an alarm signal for stopping the sputtering process in time.

Abstract: Disclosed is a planar display assembled and supported through components by making use of adhesive, mainly comprising: a transparent protection board, a display element, and an adhesive. Wherein, said display element is used as a photoelectric element (for example, an LC panel or a backlight module) forming a display. Said display elements can be glued and attached onto said transparent protection board by means of said adhesive such as Velcro, so as to reduce ordinary support elements utilized, thus significantly reducing the volume and weight of said planar display.

Abstract: A substrate is provided. The substrate includes a plurality of devices disposed in the substrate, a plurality of contact pads disposed on a surface of the substrate and electrically connected to the devices, and a surface dielectric layer positioned on the surface of the substrate. Thereafter, a surface treatment process including at least a plasma etching process is performed. Subsequently, at least a plasma enhanced chemical vapor deposition (PECVD) process is performed to form a dielectric layer on a surface dielectric layer. The PECVD process is performed in a high frequency/low frequency alternating manner. Following that, a masking pattern on the dielectric layer is formed, and an anisotropic etching process is carried out to form a plurality of openings corresponding to the contact pads in the dielectric layer. The openings expose the contact pads, and each opening has an outwardly-inclined sidewall.

Abstract: The chip-type micro-connector includes a package substrate, a micro-connector disposed on the package structure, a plurality of chips, and a cap layer disposed on the micro-connector and the chips. The micro-connector includes a connection substrate, a plurality of connecting wires disposed in the connection substrate, and a plurality of contact pads exposed on a surface of the connection substrate and respectively connected to each connecting wire. The chips are coupled to one another via the contact pads and the connecting wires. The cap layer packages the micro-connector and the chips on the package substrate.

Abstract: The chip-type micro-connector includes a package substrate, a micro-connector disposed on the package structure, a plurality of chips, and a cap layer disposed on the micro-connector and the chips. The micro-connector includes a connection substrate, a plurality of connecting wires disposed in the connection substrate, and a plurality of contact pads exposed on a surface of the connection substrate and respectively connected to each connecting wire. The chips are coupled to one another via the contact pads and the connecting wires. The cap layer packages the micro-connector and the chips on the package substrate.

Abstract: A substrate is provided. The substrate includes a plurality of devices disposed in the substrate, a plurality of contact pads disposed on a surface of the substrate and electrically connected to the devices, and a surface dielectric layer positioned on the surface of the substrate. Thereafter, a surface treatment process including at least a plasma etching process is performed. Subsequently, at least a plasma enhanced chemical vapor deposition (PECVD) process is performed to form a dielectric layer on a surface dielectric layer. The PECVD process is performed in a high frequency/low frequency alternating manner. Following that, a masking pattern on the dielectric layer is formed, and an anisotropic etching process is carried out to form a plurality of openings corresponding to the contact pads in the dielectric layer. The openings expose the contact pads, and each opening has an outwardly-inclined sidewall.

Abstract: A substrate including a plurality of contact pads is provided. Thereafter, a photosensitive dielectric layer is formed on a surface of the substrate. Subsequently, an exposure-and-development process is preformed to partially remove the photosensitive dielectric layer so as to form a plurality of openings. The openings at least expose the contact pads, and the sidewall of each opening is inclined outwardly.